This guide will demonstrate the basics of using CML Compiler through the command prompt to generate Verilog-A CMLs. For information about how the tool is used to generate CMLs for INTERCONNECT CMLs, please see CML Compiler command line interface.
It's assumed at this point that CML Compiler is already installed, for information on how to install CML Compiler, see Installing CML Compiler.
New users of CML Compiler may find it instructive to work through a step-by-step guide to understand the general workflow of the tool. For a step-by-step example of how CML Compiler is used to create a custom CML, see My first INTERCONNECT CML.
Launching CML Compiler
CML Compiler is a command line tool. Follow the instructions below to launch a terminal with the environment set-up for your CML Compiler session.
On Linux, please launch a terminal in either Bash or CSH and open Lumerical Launcher by entering:
launcher
You can either then choose to click on New Project for CML Compiler under the Products tab or launch CML Compiler from a previous project location under the Recent tab.
[[Note:]] The terminal will only be able to find the launcher if it is added to PATH after installation (see Installing CML Compiler). Advanced users can alternatively launch CML Compiler from a terminal directly as opposed to starting the launcher. |
The Command Line Interface for Verilog-A CMLs
Similar to creating CMLs for INTERCONNECT (Please see CML Compiler command line interface for INTERCONNECT CMLs for more information), the tool is accessed through the command line interface to generate Verilog-A CML. CML Compiler can be used to compile models, create QA tests and run QA tests for Verilog-A CMLs by adding the "--veriloga" option to the usual commands:
cml-compiler library --veriloga
cml-compiler library --veriloga_virtuoso
cml-compiler test --veriloga
cml-compiler all --veriloga
cml-compiler all --veriloga_virtuoso
cml-compiler runtests --veriloga
cml-compiler status --veriloga
Note: To run CML Compiler for Verilog-A CMLs, the tool needs to know the directory of Spectre and Virtuoso on the system. The first time your run CML-Compiler for Verilog-A CMLs, you will be prompted to provide these paths and these directories will be saved for the next runs. If you wish to change these paths, please change Spectre_Home and Virtuoso_Home entry in Home/<user>/.config/cml-compiler.json file.
template
Running CML Compiler with the "template" argument will create a folder and deploy the default lumfoundry_template packaged with CML Compiler installation.
cml-compiler template [-d <destination_directory>]
Note: As per our recommended practice, please run all the commands in the following sections within a foundry directory. If you do not have a foundry directory, please run the above command to create a default foundry directory. Please refer to Lumfoundry Template Directory for more information regarding our default model templates. |
library --veriloga
Running the tool with the "library" positional argument and the "--veriloga" option will produce both an INTERCONNECT CML and a Verilog-A CML, and must be done from the top-level of the foundry directory. When the tool is run with these options, it will read the library master file provided, then create both INTERCONNECT and Verilog-A elements using data within the source folder. Once the tool is finished, it will output the usual INTERCONNECT CML files described in The Command Line Interface for INTERCONNECT CMLs, as well as the following files and folders:
- /artifacts/veriloga/includeElements.scs
- /artifacts/veriloga/models
- /source/.veriloga_QA_source/<element>_verilogaData.txt
A veriloga folder is created within the artifacts folder when the library compilation tool is run with --veriloga option. The veriloga folder contains a header file includeElements.scs , which must be loaded for Verilog-A simulations. The models folder contains individual Verilog-A element model files. The end-user requires the veriloga folder contents for designs and simulations with the Verilog-A CML. For more information about using the CML in simulations, see Running Simulations with Verilog-A CMLs.
A hidden folder veriloga_QA_source is created within the source folder when the library is run with --veriloga option. The veriloga_QA_source folder contains processed element source data (*.txt files) that are needed to compile Verilog-A QA scripts. The <element>_verilogaData.txt files are generated automatically for each compiled Verilog-A element and do not need to be updated by the user. This folder should not be shared with the end user as it contains model data.
This argument supports following subcommand:
cml-compiler library --veriloga --element_list <element_name>
Using this command, you can specify which elements in the library master file you wish to build. Replace <element_name> with the names of as many elements as needed in a space separated manner.
library --veriloga_virtuoso
Running the tool with the "library" positional argument and the "--veriloga_virtuoso" option will produce both an INTERCONNECT CML and a Verilog-A CML, and must be done from the top-level of the foundry directory. When the tool is run with these options, it will read the library master file provided, then create both INTERCONNECT and Verilog-A elements using data within the source folder. Once the tool is finished, it will output the usual INTERCONNECT CML files described in The Command Line Interface for INTERCONNECT CMLs, as well as the following files and folders:
- /artifacts/veriloga/includeElements.scs
- /artifacts/veriloga/models
- /artifacts/Virtuoso_VerilogA
- /source/.veriloga_QA_source/<element>_verilogaData.txt
Two folders are created within the artifacts folder when the library compilation tool is run with the --veriloga_virtuoso option: veriloga and Virtuoso_VerilogA, and one folder is created within the source folder: .veriloga_QA_source.
The veriloga folder contains a header file includeElements.scs, which must be loaded for Verilog-A simulations. The models folder contains individual Verilog-A element model files. The end-user requires the veriloga and Virtuoso_VerilogA folder contents for circuit designs and simulations with the Verilog-A CML. For more information about using the CML in simulations, see Running Simulations with Verilog-A CMLs.
The Virtuoso_VerilogA folder contains all of the libraries and cell views that CML Compiler automatically generates for both the foundry and primitive elements. These are generated according to the description outlined in Manual Library and CDF Setup, which also provides guidelines to create these configurations manually, for advanced users.
The veriloga_QA_source hidden folder is created within the source folder when the library is run with --veriloga_virtuoso option. The veriloga_QA_source folder contains processed element source data (*.txt files) that are needed to compile Verilog-A QA scripts. The <element>_verilogaData.txt files are generated automatically for each compiled Verilog-A element and do not need to be updated by the user. This folder should not be shared with the end user as it contains model data.
This argument supports following subcommand:
cml-compiler library --veriloga_virtuoso --element_list <element_name>
Using this command, you can specify which elements in the library master file you wish to build. Replace <element_name> with the names of as many elements as needed in a space separated manner.
test --veriloga
Running the tool with the "test" positional argument and the "--veriloga" option will produce tests for both INTERCONNECT and Verilog-A models. This requires that the element source data has been processed and saved in the source/.veriloga_QA_source/ folder by using the positional argument “library” together with either “--veriloga” or “--veriloga_virtuoso” option. Once the tool is finished, it will output the INTERCONNECT QA test files described in The Command Line Interface for INTERCONNECT CMLs, as well as test scripts and netlists for validating the generated Verilog-A models:
- /source/<element>/<element>_VA_test.py
- /source/<element>/QA_veriloga/<element>.scs
Where <element>.scs is a netlist used for testing a specific element, and <element>_VA_test.py is a script which runs the QA tests. To run the tests, users can open and run the python script from INTERCONNECT, or they can be run via the command line interface using the 'runtests' positional argument.
This argument supports following subcommands:
cml-compiler test --veriloga --element_list <element_name>
Using this command, you can specify which elements in the library master file you wish to build tests for. Replace <element_name> with the names of as many elements as needed in a space separated manner.
all --veriloga
Running the tool with the "all" positional argument and the "--veriloga" option will build both INTERCONNECT and Verilog-A models, and create the QA tests for both types of CML. Furthermore, it will install the INTERCONNECT CML as a Design Kit in interconnect. This is analogous to running the following sequence of commands:
cml-compiler library --veriloga
cml-compiler install
cml-compiler test --veriloga
This argument supports following subcommand:
cml-compiler all --veriloga --element_list <element_name>
Using this command, you can specify which elements in the library master file you wish to build. Replace <element_name> with the names of as many elements as needed in a space separated manner.
all --veriloga_virtuoso
Running the tool with the "all" positional argument and the "--veriloga_virtuoso" option will build both INTERCONNECT and Verilog-A models as well as Virtuoso library files, and create the QA tests for both types of CML. Furthermore, it will install the INTERCONNECT CML as a Design Kit in INTERCONNECT.
This argument supports following subcommand:
cml-compiler all --veriloga_virtuoso --element_list <element_name>
Using this command, you can specify which elements in the library master file you wish to build. Replace <element_name> with the names of as many elements as needed in a space separated manner.
runtests --veriloga
Running the tool with the "runtests" positional argument and the "--veriloga" option will execute the QA tests for only verilog-A models. This requires that the QA tests have already been generated by using either the "all --veriloga" options or the "test --veriloga" options.
For more information on running QA tests with CML Compiler, see Running QA Tests.
status --veriloga
Running CML Compiler with the "status" argument and the “--veriloga" option will generate a list of the pass/fail state for both INTERCONNECT and Verilog-A models for the data validation, model building, testbench building, and QA test for all elements within the library master file.
Note that if the data validation, model building, testbench building, or QA testing has not been completed for a particular element, the result will show “N/A” or not available. If an element does not have a corresponding Verilog-A model, the Verilog-A status will not show up in the list.
If there are multiple library master files, CML Compiler will list the options to choose from within the current folder. If you would like to specify which one to use in the command line, this can be done using the -t option as follows:
cml-compiler status --veriloga -t path/to/datafile.xml
This argument also supports the following subcommand:
cml-compiler status --veriloga --element_list <element_name>
Using this command, you can specify which elements in the library master file you wish to generate the status report for. Replace <element_name> with the names of as many elements as needed in a space separated manner.
Finally, you can clear the status of elements using the following option:
cml-compiler status --clear_status
Any previously stored pass/fail results from data validation, model building, testbench building, and QA tests will be removed for both INTERCONNECT and Verilog-A. This option can work in conjunction with the “--element_list” subcommand described above.