Running Verilog-A simulations in Cadence Virtuoso

This article will provide a general procedure for running simulations using a Verilog-A CML, and provide three examples of how this is done in practice. Three examples of simulations which can be run using Virtuoso and Verilog-A CMLs are shown in the sections Transient Simulations and AC Simulations. Especially, in Transient Simulations, both the nominal simulation and the statistical simulation are shown.

General Simulation Procedure

1. Create Working Directory and Load Symbol Library

The end user should create a working directory for his/her projects, and launch Virtuoso from the working directory.

The end user needs to load Virtuoso symbol libraries. For information on how to load Virtuoso libraries, see Loading the Virtuoso Library for Verilog-A CMLs.

2. Create Circuit Schematic

After preparing the workspace and loading the symbol library, the user can begin their circuit design by adding symbols to a schematic. For some examples of possible circuit schematics, see the examples at the end of this article.

3. Setup simulation through Virtuoso ADE

Once schematic design is completed, the end user can set up simulation through Virtuoso ADE. To create a new ADE View from Schematic Editor, user can navigate to Launch panel and select ADE Explorer. 

3.1 Set Simulator

In the ADE window, set Simulator as spectre.

3.2 Enable "+optical"

Enabling optical Verilog-A simulations in Spectre requires using the +optical command line option. Please navigate to Setup, click on Environment, and then add +optical to User Command-Line Options.  

3.3 High-Performance Simulation Options

Checking out optical Verilog-A license requires using Spectre as the Simulation Performance Mode. Please follow the instruction below.

3.4 "ICRP" Job Mode

We recommend using ICRP job mode for Verilog-A simulations. Please follow the instruction below

3.5 (Optional) Automate Verilog-A environment setups 

Environment settings from Step 3.2 to Step 3.4 can be automated by clicking on Setup > Lumerical Verilog-A > Automate settings. It will prompt users for the changes made to ADE setup.

Finally, after loading all of the necessary models and setting environment options, the simulation is ready to be run.

3.6 Load runtime library and compact model library to ADE 

To add the runtime library and the compact model library, navigate to Setup/Model Libraries and add the following header file: 

• <foundry directory>/artifacts/veriloga/includeElements.scs 

where <foundry directory> refers to the location where CML Compiler was run to create the Verilog-A compact models. 

3.7 Set model channel wavelengths 

Lumerical Verilog-A models use global design variables, wavelength<x>, to detune wavelength-dependent performance, where <x> is the channel number. To run Verilog-A simulations, the end-user needs to set a value for wavelength<x> through ADE, as shown below. 

Transient Simulations

This guide will show how transient simulations can be done using elements from a Verilog-A CML. In this example, a simple circuit is designed based on an example Verilog-A CML:

First, users need to load the CML library into virtuoso, build the schematic as shown above. In this case, the schematic consists of a laser source, a statistical straight waveguide and a photodetector. Users should set up Virtuoso ADE as described in the Setup simulation through Virtuoso ADE, and activate tran in the ADE Analyses setup.

1. Nominal Simulation

When loading libraries, the section nominal is selected.

Run the transient simulation by navigating to Netlist and Run in the Simulation tab of the ADE window. Check the results after simulations complete. For our example, we monitored the anode and cathode output currents of the photodetector:

2. Statistical Simulation 

When loading libraries, the section statistical is selected. 

Navigate to Tools and click on Monte Carlo Tab. In the Monte Carlo setup window, Select All in the Variation option to include both process variation and mismatch variation. In addition, remember to check options: Save Waveforms (Simulation Data) and Save Statistical Parameter Data. 

Run the transient simulation by navigating to Netlist and Run in the Simulation tab of the ADE window. Check the results after simulations complete. For our example, we monitored the anode and cathode output currents of the photodetector. The output photocurrents vary due to the statistical variations of the waveguide insertion loss. 

AC Simulations

Users can perform electrical end-to-end AC analysis for electro-optical integrated circuit designs. In this example, a simple transceiver circuit is designed.

First, users need to load the CML library into Virtuoso, build the circuit schematic, as shown above, and load the model libraries to ADE, as described in the General Simulation Procedure. 

This circuit consists of a CW_Laser, a Mach-Zehnder modulator assembled by electro-optical modulators and 1x2 MMIs, and a photodetector. An AC source is introduced as a signal and is applied across the top arm of the MZM. The response voltage is measured at the cathode of the photodetector.

In schematic design, set the AC magnitude of the AC source to 1 V and set DC Voltage to the desired bias voltage (use vsin for small-signal analysis and to make sure the phase shifter operates in a linear region).

In ADE window, activate both dc and ac analyses in the Analyses setup, and set a Sweep Range for ac, e.g., from 100M to 50G in this illustration example.

In the ADE output panel, use expression to measure the output ac response and normalize it to the input trigger:

VF("/net014") / VF("/net020")

where “/net014” and “/net020” are the net names at the output and input of this example, respectively.

Run the transient simulation by navigating to "Simulation/Netlist and run", and check the simulation results.

Monitor Transient Optical Signal

Each optical schematic connection for Verilog-A components carries complex, multi-mode, and bi-directional optical signals that require multiple connections between the simulation models. To relate these multi-waveforms back to meaningful physical quantities such as power, amplitude, and phase of the optical modes, users can use either special monitoring elements or special signal post-processing features, which are introduced below.

Optical Oscilloscope

Optical_Oscilloscope (OSC) is a primitive library component that is automatically created by CML Compiler. It is designed for terminating and measuring the incoming optical signal's power, amplitude, and angle, as shown in the example below.

This model has 6 electrical outputs that return the power, amplitude, and angle, for mode 1 and mode 2. Each output is a bus where the length of this bus depends on the number of frequency channels. However, in the case of a single channel model, each output is a single wire.

Optical Meter

Optical_Meter is a primitive library component that is automatically created by CML Compiler. It is designed to be connected in series with other optical components to monitor optical signals without the use of termination, as shown in the example below.

This model has 12 electrical outputs that return the power, amplitude, and angle, for mode 1 and mode 2, in both forward and backward propagation direction. Each output is a bus where the length of this bus depends on the number of channels. However, in the case of a single channel model, each output is a single wire. 

Verilog-A Optical Monitor

Optical Monitor is an easy way to probe Verilog-A optical ports and set-up plots for optical signals, without the need to instantiate non-physical monitors to circuit schematics. This feature is available with the following products:

• Virtuoso ICADVM 20.1 ISR19 or later
• Spectre 20.1 ISR6 or later

and it requires EPDA environment setup for user's Virtuoso working directory.

To use this feature, a user should open schematic design in the ADE Explorer by right clicking on the ADE testbench name and select Open Design in Tab.

Next, in the opened schematic, a user can right click on an optical port, select Set-up Optical Monitors and Monitor Verilog-A optical signal option. This would automatically add signal monitors to the ADE Output Panel to store the signal’s potential and flow, as well as set up expressions for extracting its optical power and phase. Then, the user can go ahead running a simulation and the results will be automatically plotted once the simulation is complete.