Photonic Verilog-A for co-design with foundry PDKs – Cadence Virtuoso models

Generating custom components compatible with foundry process is critical for photonic integrated circuits. Ansys has enabled custom Ansys Photonic Verilog-A models for co-design with spice models from selected foundry PDK. To learn more about Ansys Verilog-A models please visit here. 

These models can be generated by CML Compiler using a combination of measurement and simulation data. With this flow, CML Compiler can also automatically create symbols and setup CDF to facilitate schematic design. For more information on CML Compiler please visit here.

Co-design with GF PDK using GF-compatible custom Verilog-A models

CML Compiler can generate GF-compatible Verilog-A models for co-design with spice models from GF PDK in Cadence Virtuoso which support 1 or 4 channels (wavelengths). To learn more please visit here.

Building Verilog-A models:

First, the user needs to follow the standard instructions for generating Ansys Verilog-A models using CML-compiler described here. To enable the interoperability, GF assigned third-party port convention (“A”) should be selected in the "veriloga" section in the json library file before running cml compiler as shown below: 

"veriloga":{
       "NumOfChannel":1,
       “port_convention”:{“third_party”: “A”}
}

Notes:

• GF-compatible port convention only supports 1 or 4 channels. If numbers other than 1 or 4 is set for “NumOfChannel” and third party “A” is chosen for port convention, the models will be generated with default Ansys Lumerical port convention.
• If third party “A” is not chosen for port convention, models will be generated with default Ansys Lumerical port convention.

Simulation with Verilog-A models:

Once Verilog-A models are generated they can be used for circuit as described here. Ansys GF-compatible custom Verilog-A models have their port types set to bidirectional by default. To connect Ansys models to GF models, input/output port types must be selected for the Ansys models. To modify them to be compatible with in/out GF port types, go to properties for the Ansys waveguide and modify port-types to output/input, respectively:

Notes:

• “bidirectional” port type can only be used to connect two Ansys models together
• If “bidirectional” port type is used by mistake to connect a Ansys model to a GF model, simulation would be stopped at the first time step and following messages can be found in the log: