CML Compiler generated compact models can be used for circuit schematic design and simulation in multiple platforms. INTERCONNECT compact models can be used in standalone INTERCONNECT design platform or in Virtuoso interop platform. Ansys Lumerical advanced photonic Verilog-A compact models can be simulated by SPICE solvers like Cadence Spectre. Both INTERCONNECT and Verilog-A models have their own advantages. This article will illustrate the comparison of these two different types of compact model and according to this information users can select the best choice for their application. To learn more about how these compact models are generated by CML Compiler please visit CML Compiler reference manual.
INTERCONNECT, Ansys Lumerical’s photonic integrated circuit simulator, models multimode, bidirectional, and multi-channel PICs in both time and frequency domains. The INTERCONNECT models can be used in the standalone INTERCONNECT design platform or in the Virtuoso interop platform. In both cases INTERCONNECT is the engine that solves for optical elements.
- Standalone INTERCONNECT platform: INTERCONNECT provides a schematic design environment with a circuit simulator purpose-built for photonic circuits. INTERCONNECT also comes with primitive elements and filters for simulating basic electrical circuit behaviors. Please visit INTERCONNECT page to find more about this solver.
- Virtuoso interop platform: The integration between Cadence Virtuoso, Spectre, and Ansys Lumerical INTERCONNECT enables users to co-design a complex photonic chip with electronic controls and to co-simulate the full electro-photonic circuit. In this seamless flow as shown below, Virtuoso schematic design environment is used for complete schematic capture of both electrical and photonic parts of the circuit. Virtuoso can co-simulate by simultaneously running Spectre and INTERCONNECT engines in the background and exchange data in each time step to solve for the full electronic-photonic circuit. Visit Virtuoso interoperability - Circuit Design Flows using INTERCONNECT for more details on the workflow. For an example, please see PAM4 Transceiver Virtuoso interoperability.
CML Compiler uses user-provided data to build INTERCONNECT models to be used in either of the above platforms. To facilitate photonic circuit schematic design in Virtuoso, CML Compiler also takes care of generating Virtuoso symbols. Please refer to CML Compiler GUI to learn how to build INTERCONNECT models and Virtuoso symbols for Virtuoso interop.
Verilog-A models are analog behavior models that can be solved by SPICE solvers. Photonic Verilog-A models are created to describe photonic element behaviors using the standard Verilog-A language that leverages the advantages of the mature electrical Verilog-A technologies. These models are ideal for co-designing electro-photonic circuit in EDA platforms. As shown in figure below, the complete schematic of both electrical and photonic parts of the circuit can be designed in Cadence Virtuoso, and using these photonic Verilog-A models the full electronic-photonic circuit can be simulated by Cadence Spectre.
Ansys Lumerical photonic Verilog-A models support:
- A variety of active & passive photonic components
- Consistency between schematic and layout
- Bidirectional ports
- Modeling multi-channel and multi-mode
- Small signal, noise and statistical analysis
- Modeling channel crosstalk
For an example of an electronic-photonic circuit based on Photonic Verilog-A models please see: Verilog-A PAM4 example.
CML Compiler can use user-provided data to build Verilog-A along with their Virtuoso symbols. To learn more, please refer to CML Compiler GUI.
Following is a comparison of the Ansys Lumerical INTERCONNECT and Verilog-A models. Please refer to this table to choose the proper platform for your circuit designs.
Example & Benchmark
CML Compiler uses the same source data to build Verilog-A and INTERCONNECT models. Although the physical implementations of these compact models are different, their behavior is consistent. To demonstrate the modeling accuracy, we use the following DWDM transceiver circuit as an example:
The below figure illustrates the schematic design for this electro-photonic circuit in Virtuoso:
Photonic circuit schematic can be designed using symbols of either INTERCONNECT models or Verilog-A models, and accordingly Spectre-INTERCONNECT flow or photonic Verilog-A flow can be performed to analyze the full DWDM transceiver circuit. For the electro-photonic devices, both INTERCONNECT and Verilog-A models contain electrical equivalent sub-circuit to model their electrical loading effects. Following a comparison of the circuit simulation results using these two platforms can be found:
As we can see the electro-optical co-simulation results using INTERCONNECT models and the Verilog-A model results are quite consistent.
Frequently asked questions
Q: Which model/flow runs faster?
A: Many factors might affect the overall simulation time. Just to list a few:
- Simulation time step: Cadence Spectre supports adaptive simulation time stepping, while INTERCONNECT only supports fixed time stepping, typically 0.1ps ~ 1ps, as user defined. So, ideally Photonic Verilog-A models can be run faster than INTERCONNECT models. However, Spectre’s adaptive time stepping might have difficulty converging when tiny optical time delays are introduced by models (e.g., resonators), and therefore, in some cases users might have to switch to fixed time stepping and lose the advantages of adaptive time stepping.
- Optical delay: INTERCONNECT’s typical time-step is in the range of 0.1ps to 1ps, which can accurately capture the optical delays of models with considerable simulation performance. However, enforcing the same time-step accuracy to Spectre would lead to a much longer simulation time as compared to INTERCONNECT.
- Frequency sweep: INTERCONNECT is a dedicated photonic circuit solver with full support for S-parameter analysis. Running frequency sweep through INTERCONNECT is very efficient. As compared, photonic Verilog-A models are typically built to accommodate for transient analysis. Frequency sweep for photonic Verilog-A models is typically performed in an indirect way, i.e., through DC analysis, which is very slow. The sweeping time also scales up linearly with the number of sweeping points.
- Model compilation: Verilog-A models need to be pre-compiled to C/C++ by Spectre prior to simulation, and this procedure is very time-consuming, typically linearly increase with the size and complexity of model library. In contrast, INTERCONNECT does not have such an overhead issue.
- The number of optical carrier channels and circuit complexity can also affect the simulation performance.
Overall, the simulation performance is application dependent. For the DWDM example in above, the simulation time for the Spectre-INTERCONNECT flow and photonic Verilog-A flow are comparable.
Q: Can I mix the use of INTERCONNECT and Verilog-A models in the same circuit design?
A: No. We don’t support optically connecting INTERCONNECT models with photonic Verilog-A models, because these two types of models are fundamentally different and they don’t have proper signal/information exchange to support such use cases.
Q: Which of the mentioned platforms should I use for my application?
A: INTERCONNECT and Verilog-A models have their own strengths and each platform described above is suitable for a certain application. Users based on their circuit design needs and the information provided above should choose the best option for their design. But as a rule of thumb, we can consider the following:
- INTERCONNECT: This is Ansys Lumerical’s purpose-built tool for photonic circuit simulations and provides the best platform for pure photonic circuit design.
- Virtuoso interop platform: This platform which combines the advantages of Ansys Lumerical INTERCONNECT and Cadence Virtuoso and Spectre, is a great option for electro-photonic circuit designs that include advanced photonic elements (such as lasers, non-linear effects, etc.) and require simulating the frequency domain response of the photonic circuit and the overall transient domain response of the full circuits.
- Ansys Lumerical photonic Verilog-A: Since in this platform the whole circuit is solved by SPICE solvers, it is a great option for IC designers who want to model an electro-photonic circuit and are more familiar with SPICE solvers than INTERCONNECT solver. This platform is also ideal for electro-photonic circuit designs that require to be combined with Verilog-A compact models from other vendors. This comes handy in applications where the user needs to create custom Verilog-A compact models to complement a foundry Verilog-A PDK for their desired circuit design. For an example please see Enabling Accurate Electronic-Photonic Co-Design with a Synergetic Workflow on GlobalFoundries Fotonix™ Platform.