This is an example of how the Verilog-A custom element model can be used to create a phase shifter element. The Verilog-A custom element will be useful in cases where the models offered by CML Compiler do not offer capabilities/features needed or there is no model offered that can be used for a specific photonic device. In such cases, a custom Verilog-A model can be built to model the behavior of the desired photonic device.
Note: The Verilog-A custom element model is an advanced model. Please see other phase shifter examples in lumfoundry template for more typical phase shifter implementations.
Template: veriloga_scripted_eps
Photonic Model: veriloga_scripted_element
Quality Assurance Test: None
Parameters: User defined (wg_length in this example)
Platform and Model Support
[[snippet||51087512815507]]
Required Data
The required data is collected as a struct with the following fields:
general
"general" is a struct with the following fields:
| Field | Type | Description |
|---|---|---|
| prefix | string | A string containing the prefix of the model, which will be used within a supported photonics Verilog-A platform to provide incrementing element names for each successive element that is added to the schematic. |
ports
"ports" is a struct with the following fields:
| Field | Type | Description |
|---|---|---|
| port_X | struct with the fields described in the table below | Ports defined as port_X with X being an integer, describing the user-defined ports to be added to the model. |
Each struct above consists of the following fields:
| Field | Type | Description |
|---|---|---|
| name | string | The name of the port, which will be visible to the end user. This name should be consistent with the name that will be used for netlisting. |
| dir | string | The directionality of the port, either "Input", "Output", or "Bidirectional" |
| pos | string | The side of the model which the port will be displayed on, either "Left", "Right", "Top", or "Bottom" |
| loc | number | The placement of the port on the side defined by loc, provided as a coordinate between 0 and 1. |
| order | number | The order at which the port is listed in a netlist. |
parameters
"parameters" is a struct with the following fields:
| Field | Type | Description |
|---|---|---|
| parameter_X | struct with the fields described in the table below | parameter_X with X being an integer is user-facing parameters to be added to the model. |
Each struct above consists of the following fields:
| Field | Type | Description |
|---|---|---|
name |
string | The name of the parameter. |
unit |
string | The unit of the parameter. |
default |
number | The nominal value of the parameter. |
visible_to_user |
boolean | A flag to enable/disable the parameter in the model. |
min |
number | Minimum allowed value if the visible_to_user is set to True. |
max |
number | Maximum allowed value if the visible_to_user is set to True. |
model_data
"model_data" is a struct with the following fields:
| Field | Type | Description |
|---|---|---|
| photonic_model | String |
The name of the photonic model used for this template. Please visit here for a list of all available photonic models. |
| veriloga_script_filename | string | The name of the Verilog-A script to be loaded, including the file extension (.va) |
| debug_mode | Boolean |
A flag to add unencrypted Verilog-A models for debugging. If this flag is set to 1, CML Compiler adds unencrypted Verilog-A models for this element (both CML Compiler generated shell and user-defined model) to the library to facilitate debugging process. On the other hand, if this flag is set to 0, CML Compiler will encrypt Verilog-A files for this element. |
| mode_number | number |
The number of supported modes in the user- provided Verilog-A module, which can be up to 2 modes. If the provided Verilog-A module supports one mode, CML Compiler will use the same module for the second mode response. |
ele_eq_ctk (optional) |
struct |
This is an optional input in case electrical equivalent circuit is defined by the user for the photonic module. This struct has the following entries:
|
User-defined Verilog-A script file
This file consists of the Verilog-A modules provided by the user in Verilog-A syntax with the following assumptions:
- Optical module name: Module name should match the name of the script file.
-
Optical port bit orders: Each optical port should have 4 bits for models supporting one mode or 8 bits for models supporting two modes. The order of the bits are:
0:in_RE_m1 1:in_Im_m1 2:out_Re_m1 3:out_Im_m1 4:in_RE_m2 5:in_Im_m2 6:out_Re_m2 7:out_Im_m2
Please note that the 4th to 7th bit are optional for the case the model supports 2 modes. - Electrical equivalent circuit (if applicable): The name of this module should be defined in the .json source file under “subcircuit_name”.
-
Port orders:
- Optical ports should be listed first and followed by electrical ports.
- If there are no electrical equivalent circuit, it is assumed the port order of the external photonic model is identical to the internal optical module.
- If electrical equivalent circuit is present, external photonic models and internal optical module don't need to have identical electrical port order (the connection will be described under port_connections in .json source file), but optical ports that come first need to be in the same order as the external model.