CML Compiler can generate Photonic Verilog-A models for the Synopsys platform. This enables schematic-driven design on OptoCompiler, elctro-optical simulations using PrimeSim SPICE and HSPICE and layout design for integrated electronics and photonics circuits.
User guide
Find resources on how to generate and use Verilog-A models for the Synopsys platform
- CML Compiler overview
- System requirements and installation for Verilog-A CMLs for OptoCompiler
- Generating photonic Verilog-A models for OptoCompiler
- Photonic Verilog-A model port configuration standard
- Photonic Verilog-A co-design with foundry PDKs – OptoCompiler models
Workflow Examples
Find application examples for use cases for Verilog-A models for the Synopsys platform.