Generation of custom photonic models and co-simulation with a foundry process is critical for the development of photonic integrated circuits. Lumerical CML Compiler can generate Photonic Verilog-A models from simulation and measurement for Synopsys OptoCompiler™, compatible with both PrimeSim HSPICE and PrimeSim SPICE solvers.
These models are usable alongside select foundry PDKs, which enables design of circuits that consists of both custom and foundry components. For more information on Generating photonic Verilog-A models for OptoCompiler article.
GF-compatible custom Verilog-A models
CML Compiler can generate Global Foundries (GF) compatible Verilog-A models for co-design with SPICE models from GF PDK using OptoCompiler, which supports 1 or 4 channels.
To build Verilog-A models such that it is compatible with the GF PDK, you must select the port convention before running CML Compiler. You can do so by editing the port convention to “Foundry A” in the Edit Library window.
An example is shown below.
Note: GF-compatible port convention only supports 1 or 4 channels. If numbers other than 1 or 4 is set for “NumOfChannel” and “Foundry A” is chosen for port convention, the models will be generated with default port convention.
Once the Verilog-A models are generated, ensure that the output types of the ports are changed to either input or output, from bidirectional, before connecting to a GF PDK model.
See also
Generating photonic Verilog-A models for OptoCompiler, CML Compiler overview, CML Compiler product reference manual