Lumerical INTERCONNECT and Tanner L-Edit & S-Edit driven flows - User Guide

Overview

The aim of this User Guide is to provide users the basic information they need to get started on the Siemens EDA & Lumerical INTERCONNECT layout  and schematic driven flows. For more background information on the Siemens EDA & Lumerical INTERCONNECT design flows, please visit this page. This guide assumes that the user is familiar with circuit simulation using INTERCONNECT. 

INTERCONNECT circuit simulation flow

Design flow

The diagram below shows the steps taken in INTERCONNECT as part of the Siemens EDA & Lumerical layout and schematic driven flows. Circuit and system designers use Tanner S-Edit to create their circuit schematic, and L-Edit Photonics to layout their circuit. Both S-Edit and L-Edit tools can be used to extract a circuit netlist that describes the circuit components and connections. The netlist is imported into INTERCONNECT, and a circuit is generated based on the compact model library component counter-parts with the appropriate connections. Users can then create test benches around the circuit, including sources and analyzers to simulate the behavior and performance. Once the designer has reached an optimized circuit, Calibre nmDRC is run for physical verification on the layout.

Design iteration

In layout and schematic driven flows, users commonly enter a cycle where they make adjustments to their circuit then simulate and analyze the results INTERCONNECT, then repeat. Design iteration is made straight forward by netlisting the circuit as a subcircuit, around which the test bench is created and saved. As long as the subcircuit ports do not change, the test bench used to simulate the modified circuit can remain the same.

Netlist

Introduction to netlist files

The netlist describes how circuit components are connected and what the component parameter values are. It is used to translate the Tanner L-Edit and S-Edit circuit based on the PDK components to the INTERCONNECT circuit based on CML components. Here is an example netlist file with key features highlighted.

Instances: Each component in the circuit is netlisted as a line with the following format:
InstanceName Nets ModelName Parameters=values
In the example above, the following color coding is applied:

• InstanceName (red): Unique name of the component instance
• Nets (blue): List of the nets at each of the ports. Common nets indicate that ports are connected. (Note: The port order is defined in the header file used by Tanner L-Edit Photonics and must correspond to the port order of the CML component.)
• modelName (green): name of the CML model. This model must exist in the CML for the netlist to import successfully.
• Parameters = values (black): List of component parameters and their values including the CML library of the component and the coordinates. The parameter values should be given the standard INTERCONNECT unit for the parameter. The standard unit of the CML parameter can be found from the help page of the CML component. To access the help page, add the CML component to an INTERCONNECT simulation layout, select it and right-click>“Help…”. An html page will open with tables that list the properties. In the “Default unit” column, the standard unit (“std. unit”) is indicated. For example, the standard unit for a distance is meters. Unit suffixes are also supported to provide multipliers (e.g. u = 1e-6, m = 1e-3), for example 10u = 10e-6.

The parameters include

• library: the CML library that contains the model
• lay_x= ... lay_f: Layout geometry parameters/coordinates
• sch_x= ... sch_f: Schematic geometry parameters/coordinates to be used in INTERCONNECT
• Other component parameters (e.g. radius, width for bend90)

Subcircuits: Hierarchy is introduced to the circuit using subcircuits. The subcircuit defines a parent component that is composed of children components. It is netlisted as:

.subckt SubcircuitName Ports
     InstanceLine1
     InstanceLine2
.ends

The subcircuit is closed when its ports are connected to sub-components ports by sharing a common net (see opt1 and opt2 above).

Instancing a subcircuit: Once a subcircuit is defined, it can be instanced. In INTERCONNECT, when a subcircuit is instanced, a compound element is created composed on sub-components. The following format is used:

SubcircuitInstanceName Nets SubcircuitName

How to import netlist - Starting from a blank project

Open an INTERCONNECT session. Check that your CML has been installed going to“Element Library” > “Design kits”. For more information on CML installation please see below.

Starting with a blank project, the netlist is imported into INTERCONNECT by: “File”>”Import Netlist”>”Import SPICE Netlist”. The netlist file is then located and selected. The circuit will then be generated based on the compact model library components indicated with library in the netlist.

The netlist can also be imported by script using the following command:
importnetlist("netlistFilename.spi");

NOTE: When the netlist is exported as a subcircuit without instantiation, a compound element must first be defined:

• Right click within the “::Root Element” and select “Create”> “Compound Element”
• With “COMPOUND_1” selected, go to“File”>”Import Netlist”>”Import SPICE Netlist”

To import the netlist from script:

addelement("Compound Element"); 
importnetlist("COMPOUND_1","netlistFilename.spi");

If a compound element isn’t first added, the following error message will appear:

(1) Error loading netlist: failed to import a root. No root found in the circuit.
Error loading netlist: failed to create circuit.

How to import netlist - Starting from an existing test bench

Open an INTERCONNECT session. Check that the CML is installed. Load an existing test bench project file where the subcircuit compound element is already defined. With the compound selected, go to“File”>”Import Netlist”>”Import SPICE Netlist”. The subcircuit contents are replaced by those described by the imported netlist. The name of compound instance is replaced with the SubcircuitName.

For the netlist import to be successful, the following must be true:

• The netlist file must include only the subcircuit and must NOT include the instantiation of the subciruit. If not, import will fail.
• The number of ports and the port names listed in the netlist subcircuit must match those of the compound. If not, the test bench circuit connections will become disconnected.

To import the netlist from script:

importnetlist("CompoundInstanceName","netlistFilename.spi");

If the subcircuit is instantiated in the netlist file, the following error message will arise:

(1) Error loading netlist: failed to import a root as a child of Root Element.
Error loading netlist: failed to create circuit.

Important notes on netlist import

• For any given instance, if no CML model exists with the library and modelName defined in the netlist, the import will fail.
• If a parameter is included in the netlist that is not included in the CML model, it is ignored.
• If a parameter exists in the CML model and it is not netlisted, its default parameter value is applied.

Creating a test bench

Once the netlist has been imported, a test bench is built around the subcircuit compound element to run a simulation. The test bench typically involves optical and electrical elements from INTERCONNECT’s Element Library including:

• Analyzers
• Sources
• Detectors
• Filters

Here is an example of a test bench used to measure the eye diagram of a Mach Zehnder modulator.

Save the project file (.icp) to reuse the test bench. The next time you open the file, you can import your updated netlist and rerun the simulation.

Test benches can be built, saved and loaded by script. Some useful commands are:

• load
• save
• addelement
• connect

Compact Model Libraries (CML)

About CMLs

The compact model library is a key piece in a foundry Process Design Kit (PDK). The CML is comprised of INTERCONNECT components that serve as the counter-parts to the PDK layout components. The models are calibrated to the foundry process using a combination of experimental data and component-level simulation results. The CML enables circuit-level designers to engage in circuit design flows where they can scale complexity and optimize circuit performance and yield, confident that the underlying component geometry, material composition and component design physics is represented by the CML, thereby ensuring reliable fabrication and predictable operation of the PIC.

Lumerical works with our foundry partners to produce high quality CMLs calibrated to manufacturing processes, please visit our Foundry Partners page for more information.

Advanced INTERCONNECT users wishing to implement custom compact models as part of the Siemens EDA & Lumerical integrated design flow may do so by publishing their compact model library. It is recommended that users check out the Lumerical University INT 100 course, in particular sections “Creating Custom Models” and “Creating and Working with Compact Model Libraries (CML)”.

How to install a CML

• Go to “Element Library” > “Design kits” and right click to Install…
• Set Compact Model Library Package to the path of the CML.
• Set the Destination Folder to the location where the CML folder will be installed.

Once the CML is installed, it should show up in the “Design kits” folder as shown here.

Once you close this session of INTERCONNECT, the next time you open a session, the CML library will appear.

The CML can also be imported by script with the following command:

installdesignkit(cml_file_path,cml_installation_folder, overwrite_flag);

Tanner L-Edit considerations

Netlist header file

The netlist header file is used by Tanner L-Edit Photonics to configure the netlister for a given PDK. The user selects this file during netlist extraction in Tanner L-Edit Photonics. The header file provides the link between the PDK layout component and the CML component.

For each layout/CML component, there is an entry in the header file with the following format:

.subckt  ModelName PortNames Parameters=defaultValues
.ends 

The following is critical:

• ModelName must match the CML model name.
• The PortNames must be listed in the same port order as the CML model. The port names must match those defined in the layout.
• ParameterNames must match those in the CML model. The units should be given in the INTERCONNECT standard unit for the parameter.

Here is an example header file:

.subckt  gcTE1550 optFibre optWg
.ends 

.subckt  bend90 opt1 opt2 radius=15u width=0.5u 
.ends 

Extract netlist

Header file

Select the header file provided in the Tanner L-Edit Photonics PDK package.
Uncheck “Copy contents of this file to output file”. If this is not unchecked, then the netlist is imported, the following error message will appear:

(1) Warning: empty subcircuit 'modelName' found.

Subcircuit vs toplevel

Netlist is exported as a subcircuit when the following settings are chosen:

• “Write as .SUBCKT” is checked
• “Write toplevel call to .SUBCKT” is unchecked

Netlist is exported as a subcircuit with instantiation when the following settings are chosen:

• “Write as .SUBCKT” is checked
• “Write toplevel call to .SUBCKT” is checked

Netlist is exported as a toplevel circuit when the following settings are chosen:

• “Write as .SUBCKT” is unchecked

Coordinates

Check “Write schematic coordinates (sch_x, sch_y, sch_r,sch_f) scaled by:” and define the scaling factor. A scaling factor of ~10000-40000 typically produces a circuit schematic in INTERCONNECT where the components are spread out nicely, without too much overlap and without large spacings.

If this option is unchecked, when the netlist is imported, all components will be stacked on top of each other at sch_x = 0, sch_y=0.

The option “Write layout coordinates (lay_x, lay_y, lay_r, lay_f)” controls whether the layout coordinates are netlisted. These parameters do not affect the netlist import.

Automated netlist extraction and test bench simulation 

The Ansys Lumerical macro automates the following process:

• Exporting netlist from Tanner
• Opening INTERCONNECT testbench
• Importing netlist into INTERCONNECT compound
• Running simulation

To install and run the macro:

Macro fields:

• PDK headerfile: Locate this file within the PDK. For GPIC it is found at: ...\TannerEDA\TannerTools_vxxxx.x\Process\GPIC\Production\GPIC\models\lumerical\headerFile.spi
• Netlist location: Choose a location/name to save the netlist file.
• Project file: You can do one of the following:
  • Select an existing testbench project file (.icp). For this example choose …\TannerEDA\TannerTools_vxxxx.x\Designs\Interferometer\simulations\lumerical\Lumerical_INTERCONNECT_Interferometer_Test_Bench.icp
  • Define new project file. The project file will be automatically generated and the netlist will be imported into a compound element. You can then build your test bench around this and save the file for future use.
  • Select a script file (.lsf). A variable “netlistPath” will be added to the INTERCONNECT workspace, which can be used in the script file to load the netlist.
• Compound name: Name of the compound in the test bench. Typically this should be the same as the circuit layout name.

Tanner S-Edit considerations

Extract netlist

File

The netlist will be saved to the location specified in the “To file” column. Ensure that it is saved with the correct “.spi” file extension.

Export source

Ensure the “Library” and “Cell” correspond to the circuit you wish to export, and the “View” property is set to “schematic.”

Export mode

The export mode should be set to “Flat.”

Subcircuit vs toplevel

Netlist is exported as a subcircuit when the following setting is chosen:

“Subcircuit definition”

Netlist is exported as a toplevel circuit when the following setting is chosen:

“Top-level cell”

Export control property

The export control property name must be set to “SPICE lumerical”.

Import netlist to INTERCONNECT

The netlist exported from Tanner S-Edit can be import into INTERCONNECT using the methods described in the Netlist section above. In order to have the scaling similar to the schematic in Tanner S-Edit, it is strongly recommended that the importnetlist command is used, with a scaling factor set to 0.005:

importnetlist("netlistFilename.spi",{“scalingfactor”:0.005});

Tutorial Examples

Tutorial examples are packaged in Tanner Tools.

• In Tanner L-Edit or S-Edit, go to “Help”>“Setup Examples”. A folder will then be created “TannerTools_vXXXX.X” where “XXXX.X” represents the release number.
• Navigate to “TannerTools_vXXXX.X\Designs By Type\Photonics” to find shortcuts to photonic examples folders.
• Within the example folder, navigate to “simulations\lumerical”.

For example, see “TannerTools_vXXXX.X\Designs\Interferometer\simulations\lumerical”

Application Gallery examples can be found here: 

Mach-Zehnder interferometer: L-Edit

Mach-Zehnder interferometer: S-Edit

Imbalanced MZM