The cost of CMOS image sensor pixel-based digital camera systems is being reduced through the use of smaller pixel sizes and larger fill-factors. However, CMOS pixel size reduction is only acceptable without sacrificing image quality. As CMOS pixel sizes continue to decrease, there is a reduction in image signal to noise as well as an increase in cross-talk between adjacent sensor pixels. These effects can be offset by careful design optimization through computer simulation which, at current pixel dimensions, requires a comprehensive solution involving both optical and electrical analysis.

In this topic we discuss the trends in CMOS image sensors, the implications for simulation, the types of results that can be simulated and describe the full simulation methodology to achieve them.

### Pixel Operation

A schematic of the 4T APS is shown in the following figure. In the figure, a cross-section of the active sensing region (the pinned photodiode p++ and the buried n-well) and the transfer gate are illustrated. The drain contact (SENSE) of the TX transistor can be electrically isolated, and is often termed the floating diffusion (FD). The APS can be reset by applying a pulse to RST, which will pull the FD to VDD, emptying the detector of charge and establishing an initial bias condition on that node. The FD is also connected to a common-drain amplifier, which is isolated from the column bus by the row select (RS) transistor.

In general terms, the pixel operates by collecting photo-generated charge. The photodetector is illuminated, and charge is collected in the n-well. At the end of the exposure, a pulse is applied to the transfer gate (TX), lowering the n-well barrier, and allowing the charge to move to the sense node. This charge is converted to a voltage on that node by the intrinsic capacitance of the amplifier gate and surrounding metal (V = Q/C). The voltage on the floating diffusion is read out to the column bus through the amplifier and RS gate.

A pinned-photodiode 4T APS. A cross-section of the pinned photodiode and

transfer gate is shown connected to the floating diffusion (SENSE).

### Dark Current

Two key figures of merit factor into the dark current calculation. The APS acts as a charge conversion device, representing the number of electrons generated as a voltage at the output of the amplifier. This ratio is termed the conversion gain and is commonly measured in [uV/e-]. The conversion gain can be expressed as a ratio of the electron charge to a capacitance CCG:

$$C G=\frac{q}{C_{c_{\mathrm{g}}}}$$

A second important performance metric is the dark count itself, which is the number of charges generated during an exposure period with no illumination. The dark count is often reported as the digital number (DN) which also includes the gain and non-linearity of the ADC. At the pixel level, the dark-current itself will indicate rate of charge generation, which can be translated into a count if the exposure time is known.

The dark current is an important source of both fixed pattern and temporal noise in a CMOS image sensor (CIS) pixel. In the following example, a pinned-photodiode active pixel sensor (APS) is simulated to determine the dark current density.

### Sources of Dark current

The dark current will be measured when the APS is in its reset state with no applied illumination. Consequently, the charge accumulation well will be depleted, and the internal PN junctions will be reverse biased. Multiple physical processes contribute to the recombination and generation of electrical carriers (electrons and holes), including :

- Trap-assisted (Shockley-Read-Hall) recombination
- Auger recombination
- Radiative (direct) recombination
- Surface (trap-assisted) recombination

Each of these processes can be accounted for using the material models included in CHARGE. For more information on the material database and parameters, please see the user guide entry on the material database.

Of these mechanisms, the dominant mechanisms for charge recombination and generation in silicon are the trap-assisted processes (bulk and surface), which are illustrated in the following figure.

Sources of dark current. The three dominant mechanisms that give rise to the dark current are illustrated:

(a) surface generation from trap states at the Si/SiO2 interface,

(b) trap-assisted thermalgeneration of charge in the space charge layer, and

(c) the diffusion current due to thermal generation of charge in the bulk

In the bulk case (Shockley-Read-Hall or SRH), the following formula describes the recombination rate:

$$ R_{S R H}=\frac{n p-n_{i}^{2}}{\left(n+n_{1}\right) \tau_{p}+\left(p+p_{1}\right) \tau_{n}} $$

where n and p are the electron and hole densities, respectively, n1 and p1 are related to the energetic location of the trap state (typically close to mid-gap), and τn and τp are the electron and hole carrier lifetimes, respectively. The formula for the surface recombination rate is similar, but the carrier lifetimes are replaced by an inverse surface recombination velocity.

Under reverse-bias conditions, the space charge layer of the PN junction broadens and is depleted of carriers, such that $$n, p \ll {n_{i}}$$ Under these conditions and assuming that: $$n_{1}, p_{1} \approx n_{i}$$ which is true if the trap state energy is at the intrinsic energy level, the recombination rate in the space charge layer becomes:

$$ R_{S R H} \approx-\frac{n_{i}^{2}}{n_{1} \tau_{p}+p_{1} \tau_{n}} \approx-\frac{n_{i}}{\tau_{p}+\tau_{n}}=-\frac{n_{i}}{\tau_{g}} $$

and the negative sign indicates that the recombination rate has become a generation rate: $$G=n_{i} / \tau_{g} $$

When a region of the bulk or surface is depleted by an applied voltage, it will become a source of charge, such that its current density could be described as

$$ J_{d a v k}=q W G_{t o t} $$

where W is the width of the space charge layer (SCL) in reverse bias.

Because minority carriers are swept through the SCL by the reverse bias field, their densities at the edge of the SCL will be reduced below their equilibrium concentrations. Charges generated through the same bulk process as described above are subject to diffusion, and may move along the density gradient to the depleted edge of the SCL. The diffusion current will depend on the diffusion length: the average distance that a carrier will travel before recombining. The diffusion length in turn depends on the carrier lifetime. A simple 1D model of this process gives a diffusion current (assuming a p-type neutral region):

$$ J_{d i f f}=q \sqrt{\frac{D_{n}}{\tau_{n}}} \frac{n_{i}^{2}}{N_{A}} $$

where \(D_{n}\) is the diffusivity of the electrons in silicon and \(N_{A}\) is the p-type doping concentration \( N_{A} \gg N_{D} \) Note that the diffusion current is proportional to \(n_{i}^{2}\)

To minimize the dark current, three approaches can be taken:

- minimize the depleted area,
- minimize the width of the space charge layer, or
- maximize the carrier lifetime or minimize the surface recombination velocity.

The third approach is typically a characteristic of the processing, and cannot be modified. However, typical carrier lifetimes in crystalline silicon can be very large (10s of microseconds or more). In the bulk of the device the depleted area will depend on the implant well design and distribution, which requires a tradeoff with capacity. The width of the SCL can be reduced by increasing the doping concentration to the extent that the carrier lifetime remains insensitive to that concentration.

The surface interface between the silicon and surrounding oxide poses a greater challenge. To mitigate the effect of charge generated at surface trap states, designers will look to minimize Si-SiO2 surfaces exposed to strong electric fields. In the case of the pinned-photodiode APS, this is naturally achieved through the heavy diffusion doping required to form the pinning layer. The critical region in APS design is then the path underneath the gate, which is typically lightly doped and exposed to strong electric fields.

### Angular Response

Cross-talk can be introduced both optically and electrically. Due to the wave nature of the optical input, imperfect color filtering, and alignment mismatch in the optical stack, some light will bleed into neighbouring sub-pixels, generating charge in the silicon. Additionally, charge generated from light absorbed in the target sub-pixel may also diffuse into neighbouring sub-pixels and be collected by an adjacent well. For a description of the experimental setup and optical simulation of spectral cross-talk, please refer to

In the preceding examples, the setup for the FDTD simulation is described. Two methods can be used to estimate the collected charge directly from the optical simulation. First, the power flux density through the active (or inactive) sub-pixel surface can be used to estimate the generated charge. This method ignores the light that may be absorbed below an adjacent sub-pixel, generating charge that would be collected by a sub-pixel other than the target. The second method assumes that charge generated in a certain region (a depletion region) will be collected. While this approach accounts for the distribution of absorbed light in the substrate, the size and shape of the depletion layers must be determined empirically. To accurately determine the angular response of the system, the absorbed light, which generates charge, can be used as a source in an electrical simulation with CHARGE.

In the electrical simulation, the depletion regions are defined implicitly by the distribution of dopants and the applied bias. In addition, physical processes that contribute to the generation and recombination of charge due to impurities are also accounted for. By combining the optical and electrical simulation, a complete picture of the angular response can be obtained. The angular response can be related according to the following definitions of efficiency.

### Optical Efficiency

The optical efficiency (OE) is the ratio of absorbed photons to incident photons, and is unitless. The number of absorbed photons can be calculated either from the integration of the power flux density (Poynting vector) through the pixel surface, or through the integral of the absorbed power in the substrate. The first method gives an accurate picture of the absorbed power without requiring any assumptions about the underlying volume. Please see the description of the angular response 3D with FDTD for more details.

### Internal Quantum Efficiency

The internal quantum efficiency (IQE) is the ratio of collected charge (number) to the number of incident photons, and is unitless. The IQE can be calculated knowing the source intensity and OE. In the case of monochromatic sources,

$$ I Q E=\frac{h c}{q \lambda} \frac{I_{2}}{\int_{a \Omega_{d}} P_{a b s}(\mathbf{r}) d \mathbf{r}} $$

where Iλ is the current measured in the active channel. The integral can be calculated from the OE:

$$ I Q E=\frac{h c}{q \lambda} \frac{I_{2}}{\int_{a \Omega_{d}} P_{a b s}(\mathbf{r}) d \mathbf{r}} $$

where Sin is the input source intensity in W/m2 and A is the surface area of the sub-pixel. Note that we scale the OE by the maximum possible OE for that sub-pixel (e.g. 25% for a pixel with four sub-pixels).

### External Quantum Efficiency

Assuming that each absorbed photon generates an electron hole pair, the external quantum efficiency (EQE) is simply the product of the OE and IEQ: EQE = OE x IQE. The EQE is the ratio of charge collected to total incident photons, and accounts for both optical and electrical losses. For a monochromatic source, the EQE can be converted into a responsivity,

$$ R=\frac{q \lambda}{h c} \times E Q E $$

which is measured in A/W. This is often more convenient when characterizing a photodetector.

### Transient Response

In the overview of the APS behaviour, we observed that the gate of the common-drain amplifier and connecting metals appears as a capacitance to the floating diffusion node. This allows us to simplify the circuit model for the sub-pixel, as shown in the following schematic.

The transient operation of the image sensor proceeds as follows:

- The image sensor is initialized to its reset state, with the photo-detector depleted of charge, and an initial voltage set on the capacitance CCG.
- The n-well is isolated from the floating diffusion when the transfer gate (TX) is switch off
- The floating diffusion is isolated from VDD when the transistor RST is placed in a high-impedance state.
- The photo-detector is illuminated for an exposure period T
- The charge collected in the n-well is transferred to the capacitor with a pulse applied to the transfer gate (TX).
- The capacitor converts the accumulated charge into a voltage signal, which acts as an input to the amplifier.

These steps are illustrated in the waveform below

### Contact Model

The impedance of the RST transistor can be modeled with a switched impedance (resistance) in series with the supply voltage source. The contact models in device support the simulation of series and shunt resistances and capacitances, which can be used to model the electrical characteristics of the floating diffusion connected to the drain of the transfer gate (TX). A schematic of the contact circuit used in the simulation is shown in the adjacent figure. By changing the series resistance from a low impedance to high impedance state, the behaviour of the RST transistor can be adequately modeled.

### Doping Profile

Often, the structure and doping profile for the image sensor pixel has been simulated externally using process simulation software. The structure and doping profile can then be imported into the DEVICE layout environment using the externally generated finite element doping data set (for more information, please see the topics on reading data from HDF5 sources and the script commands for doping import and structure extraction). In this scenario, it is important to verify that structure and material assignments are correct, particularly if additional operations were performed (e.g. mirroring or change of axis).

### Related publications

- F. Hirigoyen, A. Crocherie, J. M. Vaillant, and Y. Cazaux, “FDTD-based optical simulations methodology for CMOS image sensors pixels architecture and process optimization” Proc. SPIE 6816, 681609 (2008)
- Wang, Xinyang, "Noise in Sub-Micron CMOS Image Sensors", Ph.D. Thesis, Delft University of Technology