In this example, we will study the performance of a hybrid silicon-photonics photodetector. The uni-traveling carrier (UTC) photodetector (PD) is fabricated from an InP/InGaAs system, and evanescently coupled to the silicon waveguide. The optical response of the PD, including input taper, is analyzed with FDTD and CHARGE is used to simulate the electrical behaviour, including the transient response.
Background
Photo-detectors convert optical signals into electrical signals to recover the information encoded on the optical channel. These components can be accurately simulated and optimized using a combination of optical and electrical solvers. The optical properties of the photodetector are simulated using the finite-difference time-domain (FDTD) method; the local generation rate of electron-hole pairs can be calculated from optical absorbed power. This generation rate then appears as a source term in the continuity equations solved in the electrical simulation (more information).
For high-speed photodiodes, the uni-traveling carrier (UTC) design can be used to optimize transit time response by decoupling the absorbing layer from the collection layer [1]. In traditional PIN structures, carriers are photogenerated in the intrinsic (I) region, where a strong field separates them to generate the photocurrent. The velocity of the carriers is typically limited, and in most common material systems (e.g. Germanium) holes are slower than electrons, leading to a delayed and asymmetric response. By combining narrow and wide band-gap semiconductors, a single carrier type (typically the electrons) can be isolated, such that the photoresponse of the device is only dependent on the transport of those carriers. However, in comparison to PIN photodiodes, the band structure requirements of the UTC typically require III-V materials to implement, introducing additional processing requirements when integrating with silicon systems.
In this example, we base the design on the InP/InGaAs waveguide photodiode heterogeneously integrated on a silicon photonic integrated circuit [2].The referenced design is comprised of a 100nm thick InP bonding/matching layer, a 250nm thick InGaAs absorber, and a 700nm thick InP intrinsic collection layer. The material stack and the associated band structure are shown in the figure below. Photodetectors with lengths of 25um, 50um, and 150um were measured [2].
Optical Design
Simulate the optical response of the component with FDTD using the utc_pd.fsp project file. The structure can be modified to include or exclude the taper - in this example, the taper is excluded (we assume an ideal mode expander) by setting the taper length to 0um in the model properties. A mode source (λ=1.55um) is used as the input, and a construction group is used to adjust the layered structured of the PD. A generation rate analysis group is used to record the E field in the PD and calculate the optical generation rate.
The optical generation rate is averaged in the direction of optical propagation (y) and saved to a data file for CHARGE by the generation rate analysis object.
The generation rate analysis object also calculates the responsivity of the detector based on the input power and the total current calculated from the analysis volume. Adjusting the length of the detector, variation in the responsivity is observed. For comparison, the estimated responsivity from [2] is 0.8A/W. In the FDTD simulation, the amount of absorbed light is determined by the specified index of the InGaAs layer.
|
Length (um) |
Input Power (mW) |
Ideal Photocurrent (mA) |
Ideal Responsivity (A/W) |
|---|---|---|---|
|
25 |
10 |
5.8 |
0.58 |
|
50 |
10 |
11 |
1.1 |
Electrical Design and Optoelectronic Response
Steady State: Dark Current and Responsivity
Nominal dark currents were measured to be less than 10nA [2]. To simulate the steady-state behaviour of the PD, the bias is swept from -5V to 1.5V (two simulations are run: from 0 to -5V and from 0 to 1.5V). Both dark and illuminated simulations are performed. The optical generation rate is imported from the FDTD simulation for the 50um PD so running the time-consuming optical simulation can be skipped. The attached script utc_analyze_iv.lsf can be used in conjuction with the utc_steady_state.ldev project file to generate the IV curves below (Note that the y axis of the plot has been switched to log scale). From the photo-current response, the responsivity is 1.07A/W, indicating negligible recombination loss. The dark current at 5V reverse bias is set to ~1nA by reducing the carrier lifetime in the InGaAs absorbing layer. Note that given the complexity of the device a very fine mesh is required which will result in a large simulation time.
Transient Response and Bandwidth
Analysis of the transient response can be used to extract an equivalent circuit model for the photodetector that captures both transit-time delay and diode admittance (RC) [3]. First, to extract the diode admittance, we perform a small-signal analysis at varying bias voltages. The small-signal model for the diode includes a series resistance RS ~ 0 and voltage dependent capacitance C(V). The conductance is negligible (e.g. VR/Idark > 1GΩ). Each of the impedances in the diode model are interpreted as densities with respect to the surface area of the PD (e.g. capacitance per unit area), and should be scaled accordingly.
To extract the impedances, we use the admittance function for the diode,
$$ Y(\omega)=\frac{I_{o}}{V_{i}}=\left(R_{S}+\frac{1}{j \omega C}\right)^{-1} \approx j \omega C $$
The project file utc_ssac.ldev is set up to sweep the bias voltage (dc) from 0 to 5 V at the cathode contact (reverse bias operation) and the perform a small-signal analysis at the end point (5 V). The small-signal analysis is performed for a frequency range of 1 GHz to 100 GHz for a small-signal ac voltage of 0.001 V. Once the simulation is run, the small-signal ac current at the contacts can be plotted as a function of frequency. Figure below (left) shows the magnitude of the small-signal current at the anode contact. Since the admittance of the photodetector increases linearly with frequency, the current versus frequency plot is a straight line. Using the utc_ssac_extract.lsf script file we can calculate the admittance of the PD and hence the value of the capacitance as a function of frequency (figure right).
From this response, the collection layer capacitance is determined to be 0.14 fF/um2 for the entire frequency range. Additional parasitic capacitances should be included in the analysis of the RC bandwidth.
Assuming a conductive substrate, there will be a parasitic capacitance between the p+ absorption layer and the substrate (insulated by the non-intentionally doped silicon wave guiding layer and buried oxide). Assuming a 2um buried oxide and 0.7um silicon layer, a simple parallel plate capacitance estimate of Csub = 0.013fF/um2 is obtained. Note that the absorption layer is also used to contact the device (anodes), and will have approximately twice the surface area as the PD. Additionally, a static field analysis of the metal anode and cathode contacts (excluding the fields concentrated in the PD) gives a small contact capacitance contribution of Cc = 0.07fF/um (note the length units). The overall capacitance is then
$$ C=\left(C_{d}+C_{s u b}\right) A+C_{c} L $$
which has a value of approximately 80 fF for a 50um x 10um PD.
To analyze the RC bandwidth, a model of the resistance that includes the load resistance and resistive density of the contact interface is used, with values from [2]
$$ R=R_{L}+\frac{\rho_{c}}{A} $$
where RL = 50Ω and ρc = 10kΩ.um2.
The transit time limit on the bandwidth can also be evaluated using a transient simulation. Open the project file utc_pulse.ldev. Note that the simulation is configured to run in a 1D vertical slice of the PD, which improves the simulation efficiency and enables the use of a fine mesh to resolve the critical junctions. To analyze the transit time response, the global shutter is used to turn the light source (generation rate) on and off to generate an optical pulse. The settings for the shutter can be found under the "Transient" tab of the "CHARGE" solver properties.
Three current density monitors, spaced at 0.25um intervals, are used to monitor the current traveling in the collection layer of the UTC. The image below shows the transient response of at the three sample points (positions indicated in the band diagram) in the collection layer, and illustrates the propagation of the current pulse in the PD. The pulse reaches the end of the collection layer after τtr = 11ps. The dispersion in the pulse is also visible.
The transit time bandwidth can be estimated as
$$ f_{0, t r}=\frac{0.445}{\tau_{t r}} $$
and is independent of PD area. The overall bandwidth is determined from the combination of transit time and RC limits; these quantities can also be used to populate the equivalent circuit model [3]
$$ f_{0}=\left(\frac{1}{f_{0, R C}^{2}}+\frac{1}{f_{0, t r}^{2}}\right)^{-1 / 2} $$
Using the simulated capacitance and transit time in conjunction with the extracted resistance (load and contact), the bandwidth of the PD in relation to its area is found to be in good agreement with the measured response [2].
References
- Ishibashi et al., IEICE Trans. Electron., E83-C, 938 (2000)
- Beling et al., Opt. Expr., 21, 25901 (2013)
- Piels et al., Opt. Expr., 21, 15634 (2013)