pn junction diode

The p-n junction diode characteristics and operation is closely connected to the behaviour of the carriers in the junction formed at the boundary between the p-type and n-type materials. The p-n junction is also the basic building block of a variety of other devices, and the basic techniques used for the analysis of the p-n junction can be extended to other problems. Here, we study the current-voltage characteristics of an ideal silicon p-n junction diode.

Requirements

Lumerical products R2018a or newer

Backgrounds

Problem Definition

An ideal diode contains several simplifications to the properties and behavior of a more realistic device, but offers the opportunity to compare results with an analytic expression for the current-voltage relation. The ideal diode is modeled with the following approximations:

• 1D formulation,
• ideal ohmic contacts,
• an abrupt metallurgical junction,
• and no recombination.

Based on these approximations, several key properties of the device can be formulated analytically. These values are used to validate the numerical model.

Built-in Voltage

The built-in voltage for a p-n junction, assuming perfect ohmic contacts, is independent of the junction profile. Assuming that the distance between the junction and contacts is sufficient to establish local thermal equilibrium in both the p-type and n-type regions, the built-in voltage V_bi can be determined from the following equation,

$$qV_{bi} = kT \mathrm{log}\left(\frac{N_A N_D}{n_i^2}\right)$$

where k is the Boltzmann constant, N_A is the density of acceptors in the p-type region, N_D is the density of donors in the n-type region, and n_i is the intrinsic carrier concentration.

Junction Width

When an abrupt junction is formed, the width (W) of the space-charge layer can be predicted using the full depletion approximation. Using the built-in voltage determined previously,

$$W = \left[\frac{2 \varepsilon V_{bi}}{q} \left( \frac{N_A + N_D}{N_A N_D}\right)\right]^{1/2}$$

where \(\varepsilon\) is the dielectric permittivity of the material. Here, several assumptions about the dopants have been applied:

• the dopants fully ionize
• the junction is abrupt
• the carrier density is neglected in the space - charge layer (N_A p and N_D n) which is known as the full depletion approximation.

When one side of the junction is doped more heavily than the other, e.g. N_A N_D, the expression simplifies: the majority of the space charge layer is distributed where the lowest dopant concentration exists.

$$W \approx W_n = \left[\frac{2 \varepsilon V_{bi}}{q} \left( \frac{1}{N_D}\right)\right]^{1/2}$$

Diode Current

Based on the carrier injection description of current through a p-n junction, and the assumption that recombination can be neglected in the space-charge layer, the diode equation is derived,

$$I = qA\left[ \frac{D_p}{L_p}p_n + \frac{D_n}{L_n}n_p \right] (\mathrm{exp}(qV/(kT))-1) = I_0 (\mathrm{exp}(qV/(kT))-1)$$

where A is the junction area, and V is the applied voltage, The reverse bias saturation current I₀ is expressed in terms of the minority hole concentration p_n in the n-type region and the minority electron concentration n_p in the p-type region. D_n,p is the diffusivity, which is related to the mobility of the electrons and holes according to the Einstein relation,

$$D_{n,p} = \frac{kT}{q}\mu_{n,p}$$

and L_n,p is the diffusion length,

$$L_{p,n} = \sqrt{D_{p,n}\tau_{p,n}}$$

related to the carrier lifetime (due to recombination) τ_n,p. When a reverse bias voltage (V

Noting that

$$n_n \approx N_D \mathrm{\ and \ } p_p \approx N_A$$

far from the space-charge layer in the appropriate region (where the subscripts refer to that region – n-type or p-type) and using the equilibrium relation

$$ n_i^2 = np $$

we then have

$$n_p \approx n_i^2/N_A \mathrm{\ and \ } p_n \approx n_i^2 / N_D$$

A capacitance can be associated with the p-n junction due to the charge build up at the depletion layer,

$$ C = \frac{dQ}{dV_R} \mathrm{[F/cm]}$$

It can be shown that this capacitance for an ideal p-n_junction is :

$$C = \sqrt{\frac{e\varepsilon_s N_A N_D}{2(V_{bi} + V_R)(N_A + N_D)}}$$

And When N_A N_D , this expression can be simplified:

$$C = \sqrt{\frac{e\varepsilon_s N_D}{2(V_{bi} + V_R)}}$$

Modelling Instructions

This section contains detailed instructions on how to create the CHARGE project files.

Material Database

Open a blank simulation file in CHARGE. Under the Material section of the Design tab of the tabbed toolbar, click on the Electrical and Thermal button  to open the Electrical/Thermal material database. The CHARGE material database contains over 40 common Conductors (metals), Insulators (oxides), Semiconductors, and Alloys. The properties of these materials can be edited and completely new custom material can be added to the database. The "Material Properties" section in the material database has two (three for Semiconductors) tabs; Electrical Properties, Recombination (Semiconductor only), and Thermal Properties. The Thermal Properties of a material is used by the HEAT solver only whereas the first (two) tabs contain material model applicable to the electrical solver (CHARGE) only.

Temperature dependent models for many of the electrical properties of semiconductors are available. To enable a model and set the appropriate coefficients, click on the editing button, e.g.  (temperature dependence). This action will bring up the model parameter editing dialog. In this example, we will enable a temperature dependent band-gap model. Click on the  button in the 'Band Gap' properties group under the 'Fundamental' tab. In the "Edit Model Parameters" dialog that appears, enable the model, and enter the coefficients as shown in the image below. Note that the coefficients correspond to those in the equation displayed in the model parameter editor. Once the coefficients are set as shown, close the dialog by pressing OK. To visualize the temperature-dependent behavior, choose the “Visualize” option from bottom right corner of the Material Database window and select 'T' (temperature) as the first axis and check Eg (bandgap) as the result to be plotted. Select the range of temperature from 100 K to 400 K. Now clicking the 'Create Visualization' button should plot the temperature dependence of the band gap in a new window as shown below.

Click on 'Done' button to go back to material properties dialog. To complete the material setup, go to the "Mobility" tab under the "Electronic Properties". Make sure that the "Impurity" scattering model is disabled (set to None).

This is a sufficient set of parameters to model the basic behavior of silicon. All other properties should be disabled. Other semiconductors can be treated similarly. This step is now complete. The properties of the conductor (aluminum) and semiconductor (silicon) have been defined. Accept the changes by clicking OK, which closes the Material Database. Save the workspace as a new project from the "File" tab. To be consistent with the provided project file, you can name the file pn_diode.ldev.

Materials

Si (Silicon) and Al (Aluminium) - CRC must be added from the database to the materials object (only electrical properties, thermal not needed) in Objects Tree. To do this you have two options:

• Under the Materials section of the Design tab, click on New Material button . Then right click on recently added New Material under the Material Group in Objects Tree and click on Add electrical properties. This will automatically open Electrical/Thermal Material Database. Scroll it down to find Si (Silicon) from Material List and click on Select. This will add the material as Semiconductor object that includes only electrical properties of Si (Silicon).
• Click on the Electrical and Thermal button  to open the electrical/thermal material database. Select Si (Silicon) and then click on Create button as is shown below:

Geometry

This will add electrical (semiconductor) and thermal (solid) properties of silicon material into Objects Tree. After adding the properties, rename the new material to 'Si (Silicon)' by double clicking on its name or right click and then select rename. The same procedure should be followed to add Aluminum to the simulation.

The Structures section of the Design tab

can be used to introduce various types of structures into the simulation space. The available options vary from simple rectangles and spheres to complex waveguides and planar solids. In this example, we use three rectangles to define the substrate and the two metal contacts of the pn diode.

Substrate

From the Structures section of the Design tab, select a RECTANGLE to be added to the Objects Tree. Select the rectangle in the Objects Tree and click on the "Edit Properties" button  to edit the properties of the rectangle according to the following table.

Emitter

From the Structures section of the Design tab, select another RECTANGLE to be added to the Objects Tree. Select the rectangle in the Objects Tree and click on the "Edit Properties" button  to edit the properties of the rectangle according to the following table.

Base

From the Structures section of the Design tab, select another RECTANGLE to be added to the Objects Tree. Select the rectangle in the Objects Tree and click on the "Edit Properties" button  to edit the properties of the rectangle according to the following table.

Simulation Region

Click on in the Objects Tree and click the  button (on the left of the Objects Tree) to edit its properties according to the following table:

CHARGE Solver Region

In the Solvers section of the Design tab select the  to place a CHARGE solver in the simulation environment. Note that once the solver is selected, all the simulation objects (i.e. Constraints, Doping, Source, Monitors) belonging to the CHARGE solver become available under a new tab named CHARGE. Select the CHARGE object from the Objects Tree and click on the "Edit Properties" button  to edit the properties according to the following table.

Mesh Constraint

In Solver section under the CHARGE tab, press on the CONSTRAINT button  to add a Electrical Mesh Constraint to the objects tree. Select it from the Objects Tree (under CHARGE) and click on the "Edit Properties" button  to edit the properties according to the following table.

Doping

The DOPING section under the CHARGE tab provides three different types of doping objects. Two analytic doping objects (Constant, Diffusion) and one Import doping object that allows the user to import a custom doping profile from file. In this example, to create a pn junction in the diode, we will dope the entire substrate with light n-type doping and then apply a heavy p-doping on one end. Both these doping will be created using the constant type doping objects as described below.

nepi

From the DOPING section under the CHARGE tab, click on CONSTANT doping button  to add a Constant Doping Region object to the simulation. Select it from the Objects Tree (under CHARGE) and click on the "Edit Properties" button  to edit the properties according to the following table.

pwell

From the DOPING section under the CHARGE tab, click on CONSTANT doping button  to add a Constant Doping Region object to the simulation Select it from the Objects Tree (under CHARGE) and click on the "Edit Properties" button  to edit the properties according to the following table.

Monitors

bandstructure monitor

We will add a 1D bandstructure monitor in our simulation region to easily view the band profile of the pn diode. From the Monitors section under the CHARGE tab, click on the Band  button to place a band structure monitor in the simulation domain. Select the monitor in the Objects Tree and click the  button to edit its properties according to the following table.

charge monitor

We will add a 2D charge monitor in our simulation region to record the total charge in the silicon and its variation with bias voltage.  From the Monitors section under the CHARGE tab, click on the Charge

button to place a charge monitor in the simulation domain.  Select the monitor in the Objects Tree and click the  button to edit its properties according to the following table.

Boundary Conditions (Electrical Contacts)

To apply the required bias voltages to the device under investigation (pn diode) we will create two (electrical) boundary conditions to be added to the Boundary Conditions Group (available under CHARGE Solver object). There are eight types of boundary conditions available two of which are supported by the CHARGE solver. These are Electrical and Surface Recombination boundary types which can be added from the Boundary Conditions section of the CHARGE tab as shown in the screen shot below.

Emitter

Here we will create an electrical contact that will apply a bias voltage to the emitter object in the Objects Tree. Add an Electrical boundary condition from the CHARGE tab. Select it in the Objects Tree and click the  button to edit its properties according to the following table.

base

Here we will create another electrical contact that will apply a bias voltage to the base object in the Objects Tree.  Add an Electrical boundary condition from the CHARGE tab. Select it in the Objects Tree and click the  button to edit its properties according to the following table.

The project file is now set up.  Save the file using the "File" menu and run it by following the instructions provided in the  Results and Discussion section below.

Small-signal AC simulation setup

In this section, we will modify the already set up (steady-state) project file to perform small-signal analysis.

CHARGE Solver Region

Select the CHARGE solver region from the model tree and click on the "Edit Properties" button to edit the properties according to the following table.

Boundary Conditions

emitter

Select the emitter electrical contact and click the "Edit" button to edit its properties according to the following table.

base

Select the base electrical contact and click the "Edit" button to edit its properties according to the following table.

The project file is now set up. Save the file using the "Save As" option in the "File" menu and change the name to ac_pn_diode.ldev. Run the simulation by following the instructions provided in the Small-signal Analysis section.

Results and discussion

The project file used in this example is provided in the top-level page. Alternatively, the file can be created from scratch by following the steps described in the Modeling Instructions section. Once the simulation has been set up, it will look as in the following screenshot (in the XZ-plane).

There are three rectangles in the Objects Tree. The silicon substrate and the aluminum emitter and base. The silicon substrate is divided into two doped regions of p-type and n-type using the (green) constant doping boxes. The constant doping regions are defined by the dopant type (n- or p-type) and dopant concentration. The emitter and base contacts are located at the two ends of the substrate. The contacts can be associated with a range of voltage values that the simulation will sweep over to generate current-voltage plots by defining boundary conditions from the Boundary Conditions table.

In the graphical user interface (CAD), orange lines show the CHARGE simulation region. When using automatic meshing, the mesh size is based on (in order applied):

• Global constraints on edge length (min and max), which are specified by the user, and not auto-updated based on the simulation
• A global quality constraint, which specifies the minimum angle allowed in any triangle
• The distribution of dopants.

The simulation region is set up to include the substrate, anode and cathode in the XZ plane.  Since this structure has no variations in the y direction, a 1D simulation in the Z direction would also yield the same results.  The simulation region is set up for T=300 K. This temperature can be modified to model the device operation at any other temperatures.

Built in voltage and junction width are two parameters that can be quickly extracted from the simulation results. These values for an ideal junction can also be calculated analytically (using the equation on the top-level page).  We can then compare and confirm the agreement between theory and simulation.

The bias assigned to the contacts can be set by editing the boundary condition properties for base or emitter under the Boundary Condition Group in the objects tree.  The setting under the General tab of the boundary condition edit window can be modified to contain the start and stop voltage sweep values as well as the number of steps to sweep over.  Since junction width and the built in voltage are both properties of the zero-bias pn junction at thermal equilibrium, we will use a single steady-state voltage value of zero for both contacts. To do so, make sure for both base and emitter contacts, under the General tab, the bc mode is set to 'steady state' and and sweep type is chosen as 'single' with a value of 0 V. You might need to switch back to layout mode in order to change these settings. This can be done by clicking the 'Layout' button under the Simulation section of the CHARGE tab .

Bandstructure

Click the 'Run' button  so the simulation is run for zero bias.  Right click on the CHARGE object and click "Visualize bandstructure".  The visualizer window will open and show the conduction and valence bands of the silicon substrate (along with the Fermi levels).

To make your plot look like the one shown here, click the "show/hide chart setting"  button and open up the plot editor.  Select "Surface" option under "Plot type" and the "square" option under the "Axis scale options".  This will create a surface plot while changing the aspect ratio so that the x and z span are similar.  The Attributes list below the plot contains the list of results that can be viewed.  For example, the plot below shows the Ei attribute selected which plots the intrinsic Fermi level of the silicon substrate.

Built in Voltage

The built in voltage, V_bi,  is the difference between the two energy levels in the n- and p-type materials. This built in potential exists in the absence of any external voltage applied and no current is generated as a result of this potential.This value is in units of eV.

Type the following lines of script into the script prompt:

Ei=getdata("CHARGE", "bandstructure","Ei");
Vbi=max(Ei)-min(Ei);
?"Built in Voltage is " +num2str(Vbi)+ " eV";

The first line extracts the intrinsic energy level as a function of position, the second line calculates the difference between the maximum and minimum values, and the third line prints out the value of this difference corresponding to the built in voltage in units of eV.

Analytically, we have :

$$ V_{b i}=\frac{k T}{q} \ln \frac{N_{A} N_{D}}{n_{i}^{2}} $$

From the simulation setup:

$$ \begin{array}{l}{N_{A}=10^{17} \mathrm{cm}^{-3}} \\ {N_{D}=10^{15} \mathrm{cm}^{-3}} \\ {n_{i}=1.055 \times 10^{10} \mathrm{cm}^{-3}} \\ {T=300 \mathrm{K}}\end{array} $$

Substituting these values into the above equation, using kT/q = 0.025860 eV, the theoretical value of the built in voltage is calculated to be approximately 0.709 eV, in close agreement with the simulated result.

Junction Width

Open and run the script file pn_diode.lsf.  The script extracts the conduction band from the "band" monitor.  The junction width can then be extracted from the range in the z direction over which this energy level is changing until it reaches a constant value deeper into the n- or p-type material.  From the analytic equation for the junction width, described in the previous section, we can conclude that when one dopant dominates, the majority of the space-charge layer is distributed where the lowest dopant concentration exists. In this example, N_A N_D, and the expression simplifies to

$$ W \approx W_{n}=\left[\frac{2 \varepsilon V_{b i}}{q}\left(\frac{1}{N_{D}}\right)\right]^{1 / 2} $$

In the example simulation:

$$ \begin{array}{l}{N_{A}=10^{17} \mathrm{cm}^{-3}} \\ {N_{D}=10^{15} \mathrm{cm}^{-3}} \\ {V_{b i}=0.712 \mathrm{eV}} \\ {\varepsilon_{r}=11.7}\end{array} $$

Substituting these values into the above equation, W = 0.96 μm.  The actual space-charge layer extends slightly beyond 1 μm due to the inaccuracy of the full depletion approximation:  there are carriers – electrons and holes in the space-charge layer, and their populations are significant at the edges of this region, compensating the ionized dopant charge and extending the width of the space-charge layer.  The script therefore returns a junction width value of ~1.1 μm where the width is measured from where the energy level reaches 99% of the maximum value to where the energy level reaches 99% of the minimum energy value.

Right click on the bandstructure monitor and select Visualize to view the 1D bandstructure along Z axis.  Delete all attributes except Ec from the attribute list and modify the X-axis limit as shown on the figure to the right to get a better view of the conduction band in the space charge region.

Line plot of the conduction band showing the depletion width and the built-in potential

Current-Voltage Relationship

Switch back to layout mode by clicking on the Layout button . Select the "steady state" option for bc mode in the emitter contact (boundary condition). Select the sweep type to be range and and modify the values to sweep from 0.05 to 0.5 Volts in 5 steps. Run the simulation.  After the simulation is complete, right click on the CHARGE object and click 'Visualize,' then choose 'emitter.'  The visualizer window for the current-voltage plots will open.  The "I" attribute is what we are interested in.  Remove all the other attributes from the list by selecting them and then using the "Remove" button.  Click on the 'show/hide chart settings' button  at the top of the plot window to customize the plot.  Select the option to apply a "log 10y" scaling to the result.  Modify the x and y labels.  The plot of current versus voltage will look like the figure below.

Log plot of the forward bias current of the ideal diode

When the emitter bias is positive, the diode is in forward bias mode and the current is increasing exponentially with the forward bias voltage:

$$ I=I_{0}\left(e^{q V / \eta k T}-1\right) \approx I_{0} e^{q V / \eta k T} $$

where η is an ideality factor ranging from 1 (ideal) to 2 (non-ideal). Taking the log of this expression indicates that the slope of the log-scaled plot should be constant,

$$ \log _{10}(I) \propto V $$

Junction Capacitance

Another figure of merit of interest is the junction capacitance when the diode is in reverse bias. Open and run the script pn_diode_capacitance.lsf. The script sets the bias to range from -0.2 to -4 volts in 10 steps (at the emitter).  The capacitance can easily be obtained by calculating the differential charge and dividing it by the voltage change.  It will read the total charge recorded in the charge monitor and calculates the variation as a function of bias voltage.  The junction capacitance based on electrons as well as based on holes is calculated.  Using the simplified expression on the introduction page for this example, the theoretical capacitance, Cj, is also calculated and plotted on the same graph.  We can see that the values are in agreement.

Junction capacitance of the pn junction under reverse bias

Recombination effects

In setting up the simulation, we disabled bulk recombination and generation to mimic the behavior of an ideal pn-junction diode.  In reality, these phenomena affect the carrier distribution and current-voltage relationship in the device.  Switch back to layout mode by clicking on the Layout button  .  Click on the materials in the Objects Tree to modify the properties of the silicon material used in the simulation. This can be done by expanding the Si object and right-clicking on Si (Silicon) object (which contains electronic properties of Si) and selecting edit material properties.

Enable impurity scattering effect on mobility

In the "Mobility" tab under "Electronic Properties", pick the 'Masetti' model for the "Impurity" scattering of carries.

Enable impurity scattering model for mobility

Enable bulk recombination

In the 'Recombination' tab, enable the trap-assisted (Shockley-Read-Hall) and Auger recombination models.  Define the electron and hole carrier lifetimes for the trap-assisted recombination model as shown below.    For the Auger recombination model, define the carrier (electron/hole) capture coefficients as shown below.

Enable surface recombination

On the Boundary Conditions section of the CHARGE tab toolbar, click on the surface recombination button  to add a surface recombination boundary condition and select the added object under the boundary condition group in the object tree.  Then click on  button (on top of the Objects Tree) to edit surface recombination properties according to the following table

Edit the emitter contact voltage, select the sweep range type, and set the bias range from 0.05 to 0.8 volts with a step size of 0.05 V.  Run the simulation again to look at the current-voltage relationship.  After the simulation is run, right click on the 'CHARGE' object and visualize the emitter results.  Notice that with the recombination effects taken into account, the current-voltage plot (shown here on log scale) does not increase at a constant rate anymore, and exhibits three distinct regions.

Log plot of forward bias current of a real diode

You can also set the voltage to a negative value to look at the reverse bias voltage current characteristic. You will notice that now the reverse biased diode current does not reach a constant saturation value, rather the leakage current increases with voltage, which is indicative of recombination effects.  In reverse bias, the space charge layer becomes wider as the electric field increases. This effect depletes the region of carriers (hence the alternative name "depletion layer"), such that the product np

$$ R_{s r h}=\frac{n p-n_{i}^{2}}{\tau_{p}\left(n+n_{1}\right)+\tau_{n}\left(p+p_{1}\right)} $$

which reduces to

$$ R_{s r h} \approx-\frac{n_{i}}{\tau_{p}+\tau_{n}} $$

in the space charge layer (where \(n \ll n_1\), \(p \ll p_1\) and \(n_1 = p_1 = n_i \)). The negative sign indicates that carriers are now being generated by this process. These generated carriers are swept by the electric field in the space charge layer to the adjacent n- or p-type region, where they contribute to the current.

Small-signal Analysis

In this part of the example we will look at the small-signal behavior of the pn-junction diode under different frequencies of operation.  The project file ac_pn_diode.ldev provide at the top level page can be used to perform the small signal ac analysis.  Alternatively, the instructions at the bottom of the Modeling Instructions page can be used to modify the existing project file.  In the small-signal analysis, a small signal ac voltage is applied on top of the dc (steady-state) bias and the small-signal currents and voltages at the contacts are reported.  The solver region also reports the small signal charge and electric field profiles.

Reverse Bias

In reverse bias, the depletion region of the diode becomes larger and the potential barrier increases.  The capacitance at the p-n junction (junction capacitance) makes the diode behave like a capacitor.  The equivalent circuit of the diode can be expressed as a simple capacitor whose value is equal to the junction capacitance.  In the "Results and Discussion" page, we have calculated the value of this capacitance using the steady-state solver.  In this section, we will use the small-signal solver mode to calculate the junction capacitance in a much simplified manner.  We will also look at the effect of frequency on the junction capacitance.

Open the ac_pn_diode_Cj.lsf script file in CHARGE and run it.  The file will load and run the ac_pn_diode.ldev project file.  Once the simulation is run, the script will read the small-signal ac current at the "emitter" contact which is also the input contact where the small signal voltage was applied.  It will then calculate the admittance of the diode using Y = dI/dV = i/v where i and v are the small signal ac current and voltage at the emitter contact, respectively.  The real part of the admittance if the small conductance of the diode and can be neglected at reverse bias.  The imaginary part of the admittance if due to the junction capacitance and is equal to j*w*Cj, where j is the imaginary unit, w is the angular frequency, and Cj is the junction capacitance.  The script will plot the junction capacitance at different bias voltages under low frequency of operation (1 kHz) along with the analytic junction capacitance as shown in the figure below (left).  The figure on the right (also generated by the script) plots the junction capacitance under a reverse bias voltage of 2 V (-2 V at emitter) as a function of frequency.  It can be seen that at extremely high frequency of operation ( 1 GHz), the junction capacitance starts to deviate from the steady-state (low-frequency) value.

Forward Bias

The junction capacitance dominates the capacitance of a pn-junction diode in reverse bias.  In forward bias however, the charge storage capacitance or the diffusion capacitance becomes dominant.  The small-signal conductance of the diode also becomes large in forward bias as the diode turns on.  The equivalent circuit of the diode in forward bias thus becomes a parallel combination of the conductance and the diffusion capacitance.  The value of this conductance and capacitance can be again be calculated by performing a small-signal analysis.

To perform the small-signal analysis in forward bias, we will need to update the applied bias voltage in the emitter contact.  Switch back to the "Layout" mode and apply a bias voltage of 0 to 0.5 V at the emitter contact in 6 steps (step size of 0.1 V).  Run the simulation and use the script file ac_pn_diode_forward.lsf to plot the conductance and diffusion capacitance as a function of frequency (shown below).  The plot shows that the diffusion capacitance unlike the junction capacitance decreases rapidly at moderately high frequency of operation (≥ 100 kHz).

Forward bias conductance and capacitance versus frequency