Root Element (ROOT) - INTERCONNECT Element

name

Defines the name of the element.

annotate

Defines whether or not to display annotations on the schematic editor.

enabled

Defines whether or not the element is enabled.

type

Defines the element unique type (read only).

description

A brief description of the elements functionality.

library

Defines the element location or source in the library (custom or design kit).

local path

Defines the local path or working folder $LOCAL for the element.

url

An optional URL address pointing to the element online help.

temperature

Defines the temperature.

monitor data

Defines whether or not to save monitor data to memory or to disk.

monitor buffer size

The monitor memory length affects the rate at which monitor buffers fill and must be flushed. Although a small buffer size requires less memory, it increases the rate at which buffers must be flushed.

animate simulation

Defines whether or not to animate the simulation, highlighting elements which are currently running and their correspondent threads.

animation delay

Defines an additional delay for each element running time.

simulation output

Defines the type and whether or not simulation output is enable.

multithreading

The number of threads to be used in the calculation. If 'automatic', the number of processor cores will be used.

number of threads

The user defined number of threads to be used in the calculation.

maximum number of fir taps

Defines the number of coefficients for digital filter.

filter delay

Defines the time delay equivalent to a number of coefficients for digital filter.

bitrate

The output signal bitrate.

simulation input

The simulation input type. It defines the type of property used to calculate the number of samples, sample rate and time window.

samples per bit

The number of samples per bit.

sequence length

The sequence length.

time window

The duration of the generated signal. This is typically set by the global properties in the root (top-most) element.

sample rate

The sample rate of the generated signal. This is typically set by the global properties in the root (top-most) element.

number of samples

The number of samples.

output signal mode

The output signal mode.

number of output signals

The number of simulation runs, or the number of generated signals.

sample mode frequency band

The sample mode frequency band estimation. If 'automatic', the center frequency and the number of bands will be adjusted automatically. If 'single', a single band (total field) with user defined center frequency will be used.

sample mode center frequency

The sample mode reference center frequency for a single global band (total field).

THz*

*std. unit is Hz

run setup script

Defines whether to run setup script automatically or to force the setup script to run at the beginning of the simulation.

version

internal electrical equivalent

Defines if the internal electrical equivalent circuits or elements are enabled.

component id

A component identifier, defined when importing a schematic from a file.

mcs filename

The file containing a list of process design kit (pdk) names and correspondent pdk parameters.

mcs

The process design kit name.

check internal monitors

Defines whether or not to check for monitors inside of compound elements.

check disconnected ports

Defines whether or not to check for disconnected ports and relay connections in the circuit.

check analyzer sensitivity

Defines whether or not to check is signal level is below sensitivity level.

check input sample rate

Defines whether or not to generate an error if the sample rate values are not the same at the input ports of an element.

source connections

Defines how do check connections to sources. Elements not connected to a source by default are not included in the simulation (resolve). To include all elements in the simulation regardless their connections use 'ignore' option.

deadlock resolution

Defines how do resolve simulation deadlock. Insert delays to break probable deadlocks (prevent). Locate where deadlock occurs and automatically insert delays (resolve). To run the simulation and manually resolve simulation deadlock use 'ignore' option.

delay insertion

Defines whether the simulator will add delays exclusively to bidirectional ports or to any output port.