Signal aligner
Keywords
electrical, unidirectional
Ports
| Name | Type |
|---|---|
| reference | Electrical Signal |
| input | Electrical Signal |
| output | Electrical Signal |
Properties
General Properties
| Name | Default value | Default unit | Range |
|---|---|---|---|
|
name Defines the name of the element. |
Signal Aligner | - | - |
|
annotate Defines whether or not to display annotations on the schematic editor. |
true | - | [true, false] |
|
enabled Defines whether or not the element is enabled. |
true | - | [true, false] |
|
type Defines the element unique type (read only). |
Signal Aligner | - | - |
|
description A brief description of the elements functionality. |
Signal aligner | - | - |
|
prefix Defines the element name prefix. |
ALN | - | - |
|
model Defines the element model name. |
- | - | - |
|
library Defines the element location or source in the library (custom or design kit). |
- | - | - |
|
local path Defines the local path or working folder $LOCAL for the element. |
- | - | - |
|
url An optional URL address pointing to the element online help. |
- | - | - |
Standard Properties
| Name | Default value | Default unit | Range |
|---|---|---|---|
|
start time Time instant to start the signal analysis. |
0 | s | [0, +∞) |
|
stop time Time instant to stop the signal analysis. |
1024/%sample rate% | s | [0, +∞) |
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Implementation Details
The Signal Aligner aligns the "input" signal according to the "reference" signal and ideally, the "output" signal matches the "reference" signal. The time instants to start and stop ("start time" and "stop time") the signal analysis are set to 0 s and 1024/%sample rate% by default. User may need to vary the start and stop time depends on different simulation conditions.
The following figure shows the circuit in the example file signal_aligner.icp:
In the circuit, the NRZ signal is separated into two branches and the lower branch is delayed by a Delay element for 100 ps. Then after the Signal Aligner, the output signal will be aligned based on the "reference" signal and the delay will be corrected. The input, reference and output signals are shown in the figure below: