Display digital signals in time domain
Keywords
analyzer, digital, unidirectional, bidirectional
Ports
| Name | Type |
|---|---|
| input | Digital Signal |
Properties
General Properties
| Name | Default value | Default unit | Range |
|---|---|---|---|
|
name Defines the name of the element. |
Logic Analyzer | - | - |
|
annotate Defines whether or not to display annotations on the schematic editor. |
true | - | [true, false] |
|
enabled Defines whether or not the element is enabled. |
true | - | [true, false] |
|
type Defines the element unique type (read only). |
Logic Analyzer | - | - |
|
description A brief description of the elements functionality. |
Display digital signals in time domain | - | - |
|
prefix Defines the element name prefix. |
LGCA | - | - |
|
model Defines the element model name. |
- | - | - |
|
library Defines the element location or source in the library (custom or design kit). |
- | - | - |
|
local path Defines the local path or working folder $LOCAL for the element. |
- | - | - |
|
url An optional URL address pointing to the element online help. |
- | - | - |
|
icon type Defines the icon or element symbol view option. |
small | - | [small, medium |
Standard Properties
| Name | Default value | Default unit | Range |
|---|---|---|---|
|
limit time range Enables setting the time range( start/stop) of the analysis. |
false | - | [true, false] |
|
start time Time instant to start the signal analysis. |
0 | s | [0, +∞) |
|
stop time Time instant to stop the signal analysis. |
1 | s | [0, +∞) |
Simulation Properties
| Name | Default value | Default unit | Range |
|---|---|---|---|
|
input signal selection Input signal selection option. |
last | - | [last, index |
|
input signal index The signal index to analyzed. |
1 | - | [1, +∞) |
|
include delays Defines whether inserted delays should be included as part of the signal or not. |
false | - | [true, false] |
Display Properties
| Name | Default value | Default unit | Range |
|---|---|---|---|
|
refresh Defines whether or not to update display and annotations during the simulation. |
true | - | [true, false] |
|
refresh length Defines how ofter to update the element. This is the minimum number of new data values available at the element input port that will trigger the element update. |
16 | - | [0, +∞) |
|
limit display memory Defines whether or not to limit the number of values displayed in the element display. |
true | - | [true, false] |
|
display memory length This is the number of data values used to update the display and annotations during the simulation. |
2048 | - | [2, +∞) |
Results
| Name | Description |
|---|---|
| digital signal | The input signal waveform. |
| bitrate | The input signal bitrate. |
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Implementation Details
The logic analyzer displays digital signals in time domain according to its bitrate and sequence length. For detailed information, please see the example file Logic_Analyzer.icp, the following figure shows the system in the example file.
There are two results can be displayed and annotated after run the simulation, the "digital signal" and the "bitrate", respectively. Following is a figure shows the "digital signal" waveform.