Signal Integrity Analysis in a Co-packaged Optics System using RaptorX-Spectre-INTERCONNECT Interop

INTERCONNECT Virtuoso ADE Interoperability Photonic Integrated Circuits - Circuit Communications

In today’s high-speed data communication networks, co-packaged optics (CPO) systems have become a key innovation for addressing the growing need for bandwidth and efficiency. By combining photonics and electronics into a single package, these systems provide notable benefits, including lower latency and reduced power consumption. However, maintaining signal integrity in such densely integrated setups is a significant challenge, making signal integrity analysis crucial. This article examines a simple generic system, consisting of an electrical (driver) die driving a silicon photonic modulator on a photonic die through RF interconnects, to illustrate the workflow for signal integrity analysis in CPO systems using Ansys Lumerical INTERCONNECT, Ansys RaptorX and Cadence Spectre. The focus is specifically on the impact of RF interconnects on the high-speed performance of the CPO system.

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Overview

Understand the simulation workflow and key results

In this example, we consider a simplified CPO system consisting of high-speed RF interconnects to operate the modulators at high speeds. These interconnects introduce parasitic resistances, inductances and capacitances, which degrade signal quality, and can lead to impedance mismatch, resulting in unwanted reflections. Additionally, the associated electromagnetic interference and crosstalk from adjacent channels further degrades the signal quality. These issues become more pronounced at high speeds, posing significant challenges to maintaining signal integrity. Therefore, thorough signal integrity analysis is crucial to ensure overall functionality and performance.

The following figure presents the full schematic of the system, including the photonic components (PAM4 modulator, laser, and detector) and the electrical driver circuitry. The PAM4 modulator block also includes a provision to account for the effect of the RF interconnects/connectors, which is detailed further in Step 2 of the "Run and Results" section.

Full Schematic.png

In this example, we use three different tools: Ansys RaptorX for calculating the S-parameters of the RF interconnect, Ansys INTERCONNECT for photonic circuit simulation, and Cadence Virtuoso/Spectre for simulating the driver IC and other electrical circuits.

This example is divided into four steps, outlined below.

Step 1: Initial setup

Complete the initial setup, which includes extracting the simulation package, configuring the EPDA environment, and integrating RaptorX into the Virtuoso environment.

Step 2: Extract the S-parameters for the RF interconnects/connectors

Use RaptorX to perform the EM modelling of the RF interconnects/connectors for extracting the S-parameters.

Step 3: Update the extracted S-parameters to the schematic design

Incorporate the extracted S-parameters from the previous step into the schematic design.

Step 4: Netlist and run co-simulation

Finally, perform electro-optical co-simulation (CoSim) using Spectre-INTERCONNECT interop, and evaluate the performance of the CPO system with and without the effects of RF interconnects/connectors.

Run and results

Instructions for running the model and discussion of key results

Step 1: Initial Setup

Extract package and cd to /EIC_PIC_SI/coSimulation (working directory)
Environment setup
1. Install EPDA environment to the working directory. For detailed steps, please refer to the Install EPDA environment to a new working directory – Ansys Optics page.
2. Set up RaptorX environment to integrate with Cadence Virtuoso:
  1. Locate the "data.reg" file at <Helic_installation_loc>/<helic_version>/tools/cds/setup/data.reg
  2. Copy this "data.reg" file to your working directory, or have your CDS manager install it at: <virtuoso_installation_loc>/share/cdssetup/registry/data
  3. Set the "HELIC_ROOT" environment variable:
    setenv HELIC_ROOT <Helic_installation_loc>/<helic_version>
  4. Set the "HELIC_PDK_ROOT" environment variable:
    setenv HELIC_PDK_ROOT <path_to_extracted_package>/EIC_PIC_SI/references/RF_connector
  5. Locate the ".cdsinit" file at <Helic_installation_loc>/<helic_version>/tools/cds/setup/.cdsinit
  6. Append the ".cdsinit" file found in step v. to the local ".cdsinit" file under <path_to_extracted_package>/EIC_PIC_SI/coSimulation or add the following line to the local ".cdsinit" file:
    load(strcat(getShellEnvVar("HELIC_ROOT") "/tools/cds/setup/.cdsinit"))

A successful integration of RaptorX into Cadence Virtuoso environment using the above instructions enables the menu choice “HelicCentral” in the Cadence Virtuoso CIW window as shown below.

Step 2: Extract the S-parameters for the RF interconnects/connectors: from Virtuoso layout design

Once the environment is set up as explained in Step 1, the next step is to extract the S-parameters for the RF interconnects/connectors.

Launch Virtuoso from the working directory and open Library Manager (Tools/Library Manager)

Load the "analogLib", "basic", and "opticalLib" libraries. These libraries can be added using “Library Path Editor” which can be accessed from the Library Manager using Edit/Library Path.... The paths to the libraries are:
<virtuoso_installation_directory>/tools.lnx86/dfII/etc/cdslib/basic
<virtuoso_installation_directory>/tools.lnx86/dfII/etc/cdslib/opticalLib
<virtuoso_installation_directory>/tools.lnx86/dfII/etc/cdslib/artist/analogLib

In the Library Manager, expand the "EIC_PIC_signal_integrity" library group. Navigate to the "PhotonicModulator" library within this group, select the "PAM4_sp_element" cell, and double-click on the "schematic" view to open the schematic design.

In the schematic, the highlighted regions can be used to connect a 16-port element, representing the RF interconnects, via wires provided on the left.

Launch HelicCentral from Virtuoso CIW (HelicCentral/Start)
Select the RaptorX option from HelicCentral

From the left panel of the HelicCentral interface, different tools (VeloceRF™, RaptorX™, RaptorH™, Exalto®, and RaptorQu™) can be invoked by simply selecting the corresponding button. These buttons also control the license checkout and activation of the corresponding tools. To invoke RaptorX tool, simply select the RaptorX button from the left panel.

RaptorX provides three different extraction methods under the “Extract” tab: "Extract Layout", "Custom Device", and "Extract GDS". "Extract Layout" represents the main extraction flow of RaptorX and integrates with Cadence Virtuoso or Synopsys Custom Compiler. "Extract GDS" uses a GDS representation of the layout design as input, rather than an equivalent Cadence or Synopsys layout view, and utilizes a layer map file to resolve layer mapping between the streamed-out data and the technology definition data. Additionally, the "Custom Device" option initiates the RaptorX extraction flow, supporting third-party LVS checking and the back annotation of RaptorX models to the extracted view or netlist.

S-parameter extraction for RF interconnects/connectors: extract from Virtuoso layout design
1. From Virtuoso Library Manager, navigate to the "RF_connector" library, select the "Top_Interposer" cell, and double-click on the "layout" view to visualize the layout design of the RF connectors/interconnects.

The layout view of these interconnects is shown in the figure below, with various magnified views for clarity. This layout features 8 interconnect lines, also known as connections or nets, which guide the signal from the electrical/driver die to the photonic die. The interconnect lines are created in the M1 layer and are connected to the corresponding pads in the M6 layer via vias that traverse through multiple metal layers: M1, M2, M3, M4, M5, and M6.

1. In HelicCentral, select the "Extract Layout" tab under the "Extract" tab at the top and click "Extract". This will open a dialog for selecting the current cell view.

1. From the "Select Current CellView" dialog, select the layout view opened in step a. and click ok.
2. Select "Interactive Pin Placement" in the popup window. If you choose to use text labels, please skip steps [e.-g.].

1. The layout design will show up in KLayout. When prompted to choose whether to use auto pin naming, select "No".

Interactive Pin Placement mode offers two options for pin naming. Selecting "Yes" in the pop-up window enables the auto pin naming feature, while selecting "No" allows for manual pin selection and naming through KLayout. In the manual approach, the user clicks on each pad and enters the corresponding pin name. This demonstration focuses on the manual approach using KLayout.

1. Left click on the pad, then name the pin in the pop-up prompt.

Note that the pin names defined in this step will be used as port names in the RaptorX generated Virtuoso symbol later.

NOTE: If you click on the area that has structures on multiple layers, a layer selection window will pop up. Please make sure that you have selected the layer on which the pad is located, i.e., in this example, M6.

A Middle mouse click will bring up a dialog with a list of pins that have been placed so far. You may remove any misplaced or misnamed pins, then continue with pin placement.

Here, for example, after placing three pins (Line1_In, Line2_In, and Line3_In), if we click the middle mouse button in the layout visualization region, the following dialog will appear. In this dialog, we can see a list of the placed pins and remove any misplaced or misnamed ones.

1. Once the pin placement for all the 16 pads is completed, right click in the layout visualization region to end the pin placement phase and begin the modeling phase.
2. In the modeling phase, the "Nets Advanced Options" window will show up, where you can check the selected pins and corresponding nets, highlight them in KLayout, and set simulation options individually for each net. In this example, we will keep all the default settings. After finishing all the setup, click Finish to kick off the simulation.

The "Nets Advanced Options" window list all the nets with corresponding properties/settings. The "Mode" column shows the simulation mode of the corresponding nets. The "Set" buttons under "Advanced" column open the "Nets Advanced Configurations" setting on the right, which can be used to control the Extraction Mode, Meshing Frequency, and Edge Mesh for each individual net. The "Highlight" column gives the option to highlight the corresponding net within the KLayout.

1. Click the "Jobs" tab in the left panel of HelicCentral; it displays the status and history of all the jobs.

1. Once the job status shows "Finished", return to the Virtuoso Library Manager. You will then notice that RaptorX automatically creates a new cell view, "Top_Interposer_VRX", which contains the required S-parameters for running the PAM4 co-simulation.

The "Job Management" window also provides access to the ANSYS MeshViewer. Users can right-click on a job and select "View Mesh" to open the ANSYS MeshViewer, allowing them to visualize the mesh used by the solver at the individual net level.

Step 3: Update schematic with calculated S-parameters: using calculated S-parameters element

From Virtuoso Library Manager, navigate to the "PhotonicModulator" library, select the "PAM4_sp_element" cell, and double-click on the "schematic" view to visualize the schematic design.
Press "I" in the schematic visualization area. In the dialog that appears, select the "RF_connector" library, the "Top_Interposer_VRX" cell, and the "symbol" view. Then, connect this 16-port element to the wires placed on the left side of the schematic. (Note: This option is only available when the S-parameters are extracted from the Virtuoso layout view)

Check and save the schematic design.

Step 4: Netlist and run co-simulation

From Virtuoso Library Manager, navigate to the "Cosim_testlib" library, select the "tb_PAM4" cell, and double click on the "maestro" view to open the ADE window.
From the top panel of ADE, select Setup/Model Libraries... and update the path to the model library to EIC_PIC_SI/references/gpdk045/models/spectre/gpdk045.scs.
Add the S-parameter model to the model library from
EIC_PIC_SI/references/designs/oa/RF_connector/Top_Interposer_VRX/typ_27C_sp_scs/spice.spc.
(Note: This step is mandatory when using the S-parameter symbol automatically created by RaptorX in the schematic design.)

Model Library setup.png

In the ADE window, under "Simulation" menu, select "Netlist and Run" to start the simulation.

Once the simulation is complete, the results will be automatically plotted. On the left side of the waveform visualizer, the waveforms applied to the first and second sections of the top and bottom phase shifters are displayed. On the right side, the electrical and optical eye diagrams are shown. The waveforms on the left appear significantly distorted, and the eye diagrams on the right show very small eye openings, indicating signal degradation due to integrity issues.

Compare with the simulation results that ignore the effect of RF connectors.
1. From Virtuoso Library Manager, navigate to the “Cosim_testlib" library under "EIC_PIC_signal_integrity", select the "tb_PAM4" cell, and double-click on the "schematic" view to visualize the schematic.
2. Select the PAM4 element and press Q, switch the cell view entry from "PAM4_sp_element" to "PAM4_no RF".
3. Save and check the schematic design, then return to the ADE window. Click "Netlist and Run" under "Simulation" menu to rerun the simulation.

The eye opening without the effect of RF connectors is significantly better in comparison to the case where the effect of RF connectors was considered. However, in practice, RF connectors do impact performance, and hence the effect can’t be ignored, making it crucial to study the signal integrity of the system for better designing and placement of interconnects and dies.

NOTE: Alternative approaches to Step 2 and Step 3 can be used instead of the primary methods discussed earlier. The choice of method is based on user preference. The alternative Step 2 involves extracting S-parameters from a GDS file rather than from a Virtuoso layout design. For alternative Step 3, you can use an S-parameter file with an existing 16-port element (used to model interconnects/connectors) instead of generating a 16-port Virtuoso element for this purpose. Please refer to the Appendix for more details.

Important model settings

Description of important objects and settings used in this model

The "Settings" tab in "HelicCentral" window consists of the following three sub-tabs to access various extraction options.

Extraction: Under the extraction subtab, you can choose between RaptorX Electromagnetic or RaptorX Parasitic. Since we need S-parameter for this example, the relevant extraction mode for us is Electromagnetic, which offers two different modes: Golden EM and Fast EM. Golden EM provides the highest accuracy with detailed meshing, ideal for very sensitive high-frequency applications, but it is the most resource-intensive in terms of CPU time and memory. Fast EM, on the other hand, allows for accelerated electromagnetic extraction and offers a good balance between accuracy and computing resources. Here, we use the Fast EM mode for a quick simulation. The maximum frequency of interest is set to 20 GHz, which further affects the meshing. The temperature is set to the default 27 degrees Celsius. The resource settings can be controlled according to the available computational resources.

Advanced: The advanced tab controls special modelling engine settings such as meshing, etching, substrate network extraction and shrink factor for half-node process designs. We use the default settings here.

Outputs: The output tab specifies output model format (Netlist, S-Parameters (SP), or Rational function model (RFM)) and mesh visualization options.

Updating the model with your parameters

Instructions for updating the model based on your device parameters

This example shows the workflow to perform signal integrity analysis of a co-packaged optics system. Although a PAM4 transceiver with RF interconnects to connect the electrical driver die to the photonic die is used here to demonstrate the workflow, the user can apply the methodology described in this example to their circuit of interest with their own libraries.

Taking the model further

Information and tips for users that want to further customize the model

There is a trade-off between the accuracy and time which can be controlled via the mesh setting. The user has the option to control the mesh complexity and hence the accuracy of the results. However, increasing accuracy comes at the cost of computational resources and time required to run the simulation.

Additional resources

Additional documentation, examples and training material

Related Ansys Innovation Courses

Appendix

Additional background information and theory

Alternative for Step 2: Extract the S-parameters for the RF interconnects/connectors: from a GDS file

Instructions 1-5 are identical to those provided under Step 2 earlier, and therefore are not repeated here.

S-parameter extraction for RF interconnects/connectors: extract from a GDS file
1. In HelicCentral, select "Extract GDS" tab under "Extract" tab on the top.
2. Select the GDS file and layer map file by clicking the three dots "…" following the corresponding entries and click on Extract.
  GDS File: EIC_PIC_SI/references/RF_connector/Die_To_Die_Interposer_Sig_Only.gds
  Layer Map File: EIC_PIC_SI/references/RF_connector/procInfo/stream.layermap_hc_rxgds.
  NOTE: You can also view your selection by clicking on "View".

The remaining instructions are same as provided in Step 2 earlier. After following all these steps, you will see the extracted s-parameter files in the designated output folder:
<output_directory>/<typ_temperature>/Die_To_Die_Interposer_Sig_Only_typ_27C.sp

Alternative for Step 3: Update schematic with calculated S-parameters: update S-parameters file in the 16-port element

From Virtuoso Library Manager, navigate to the "PhotonicModulator" library, select the "PAM4_nport" cell, and double click on the "schematic" view to visualize the schematic.
Select the 16-port element in schematic design and press Q to edit object properties.
Type in or browse to import the S-parameter file (*.sp) to the S-parameter data file entry. This file can be found at:
<output_directory>/<typ_temperature>/Die_To_Die_Interposer_Sig_Only_typ_27C.sp

Check and save the schematic design

NOTE: If you choose to use alternative Step 2, please ensure you complete the following before proceeding to Step 4: In the "Virtuoso Library Manager", navigate to the "Cosim_testlib" library under "EIC_PIC_signal_integrity", select the "tb_PAM4" cell, and double-click on the "schematic" view to open it. Then, select the PAM4 element, press "Q", and change the cell view entry to "PAM4_nport".