Building a compact model library takes the library and element source data and converts them into compact models that can be used in INTERCONNECT or other platforms such as Synopsys OptoCompiler and Cadence Virtuoso. There are two steps: validating the source data and building the compact models.
Validating Source Data
To validate the source data in your library:
- Select the Library master file that includes the elements you would like to validate.
- Select the elements you would like to validate in the Element Status Center. To select all of the elements, enable the Select all/Unselect all checkbox below the element list.
- Press the Validate button in the toolbar.
After the Validate button is pressed, the element source data will be validated to ensure all required data is included in the correct format. The results of the validation will be printed to the Output. Once all elements have been validated, the status indicator in the Validate column of the Element Status Center will either be colored green to indicate the element passed validation, or red to indicate the element did not pass validation.
Building Compact Models
After the source data has been validated, the compact models can be built. The source data will be automatically validated before building the compact model.
To build compact models from the source data in your library:
- Select the Library master file that includes the elements you would like to build.
- Select the elements you would like to build in the Element Status Center. To select all of the elements, enable the Select all/Unselect all checkbox below the element list.
- If you would like to create Verilog-A elements, change the model toggle to Verilog-A in the toolbar. Verilog-A models can only be generated in Linux.
- Edit the library by clicking on the Edit Library button in the toolbar, and set platform, number of channels, symbol generation, and port convention as required.
- Press the Build button in the toolbar.
After the Build button is pressed, the element source data will be validated to ensure all required data is included in the correct format. If the element passes validation, the element will be compiled into a compact model.
The results of the validation and build process will be printed to the Output. Once all elements have been built, the status indicator in the Validate and Build columns of the Element Status Center will either be colored green to indicate the element was successfully validated and built, or red to indicate the element was not validated or built successfully.
The compact model files are saved in the artifacts folder of the library source directory.
In the case of building Verilog-A models, the following files are generated:
- Model files in /models/: Verilog-A files for the compiled compact models.
- Primitive files in /primitives/: Optional Verilog-A elements that can be used for testing.
- .I (OptoCompiler) or .csc (Virtuoso) files: Library files to include in OptoCompiler or Virtuoso to load the library
- CDF mapping JSON file (CDF_setup_reference.json) in /<platform>_VerilogA/: JSON file used as a reference to configure element parameters (CDF) manually
- Symbols in /<platform>_VerilogA/: Symbols for the selected platform, if you selected symbol generation when building the library.
Note: When using primitive/model pairs in simulations, ensure they are both built with the same number of channels.
For further information on the directory structure, see Library Source Directory Structure.
These files can then be installed in your desired platform and used for circuit simulations.