Thermally aware photonic circuit simulation of a WDM transceiver – Icepak integration

In this example, Ansys Lumerical INTERCONNECT’s capability in modeling Photonic Integrated Circuit (PIC) is combined with Icepak’s powerful thermal simulation capability to simulate and design a Wavelength Division Multiplexing (WDM) transceiver while accounting for the heating from the other domains in the package (e.g., Electronic Integrated Circuit (EIC), Printed Circuit Board (PCB), etc.).

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Overview

Understand the simulation workflow and key results

This article is based on an example of a six-channel WDM system. The system utilizes Co-packaged optics (CPO) design and contains both optical and electrical devices. The performance of the silicon photonics element can be affected by the temperature variation in the compact CPO as a result of the heat generated by EIC and PCB. Here we aim to 1) understand the temperature distribution in  the CPO through thermal simulation and 2) find the optimum position of the WDM elements on the board to mitigate the adverse effect of heating by the electrical components.

First, the thermal simulation of the full package is done using Icepak. The temperature map of the photonic (silicon) layer can then be generated and exported for photonic circuit simulation.

Next, the temperature map is imported into INTERCONNECT. INTERCONNECT runs several simulations with different locations of the optical components on the wafer. Figure of merits like eye diagram and Bit Error Rate (BER) are analyzed based on the sweep results to decide the best allocation of the optical components on the wafer.

Step 1: Thermal simulation in Icepak

Icepak calculates the temperature on the package when operating and exports the silicon wafer mesh coordinates and corresponding temperature.

Above shows an example of the PCB board design for the thermal analysis. The green layer is the Silicon wafer and the brown layer is the PCB board. The connection between the PCB and the Silicon wafer is using ball grid arrays. The transparent box is the EIC on top of the board and the EIC is used as the heat source to initiate the thermal analysis of the board. In this example we treat the EIC as an uniform heat source, and user can also load in power map for the EIC for more sophisticated thermal analysis.

For this thermal simulation, the EIC heating comes from Chip Thermal Model (CTM) and the Joule heating are imported from SIwave. On the bottom of the wafer, temperature is set at 50 ℃ and natural convection Heat Transfer Coefficient (HTC) is set on the top.

[[Note:]] To export the temperature map, users need to use the “Write Thermal Loads” ACT extension with Icepak.

Step 2: Circuit simulation in INTERCONNECT

The WDM transmission link is used as the testbench in INTERCONNECT. INTERCONNECT imports the temperature map that was generated in the previous step and uses a script to allocate the WDM system on the wafer. The temperatures of the optical components in WDM circuit are set based on the temperature map of the wafer. The compact models (generated by CML Compiler) used in the simulation are temperature sensitive and adjusts the performance of the models according to the updated temperatures. Then INTERCONNECT runs the circuit simulation and gets the figure of merit results (BER and eye diagram). By comparing the results for different locations (and consequently different temperature), we can figure out the optimum position of the PIC elements.

Run and Results

Instructions for running the model and discussion of key results

Step 1: Thermal simulation in Icepak

1. Open and run the file [[Thermal_simulation.aedtz]] in Icepak. use the “Show/Hide ACT Extension” button to show the ACT extensions if they are hidden.
2. Navigate to the “Write Thermal Loads” extension and setup the “Destination Folder” to save the temperature map file.
3. Click “Finish” in the extension and the temperature map of the .txt format will be saved to the specified destination folder.

The temperature of the whole board is showing below. The temperature map file saves the board mesh (x, y and z coordinates) and its corresponding temperature.

Step 2: Circuit simulation in INTERCONNECT

Circuit performance with default allocation of the optical board on the wafer:

1. Open the file [[WDM_6_channel.icp]]. This is the testbench that contains a six-channel WDM circuit. The building components come from the Demo_CML compact model library (CML).
2. Install the [[Demo_CML.cml]] to the Design Kits folder in the Element Library then refresh (File / Refresh) the file.
3. Open and run the [[temp_set_up.lsf]] script in the Script Editor. This script will call the [[load_temp_map.lsf]] script and set the temperature to the components in the circuit based on the x- and y-shifts of the optical board on the whole wafer.
4. Run INTERCONNECT simulation and plot eye diagrams for the 6 channels and note the BER value in the Eye Diagram analyzer.

The [[temp_set_up.lsf]] script generates the temperature map of the wafer for a specified z-location. Since the optical components height are short compares to the whole board, we assume uniform temperature distribution in the z-direction for the optical components and fix a z-value to generate the temperature map in the script. The optical board will be represented by the dark blue box on the plot so we have the vision of how the optical board is allocated on the wafer and the operating temperature of the optical board in that location.

With the default settings, the optical board is placed at 0 mm and 0 mm place on the wafer where the operating temperature is around 60 Celsius degrees. This is one of the best allocations of the optical board given other routing restrictions and taken temperature into consideration (the tuning power of the ring models are the minimum). Following are the eye diagrams and BER for channel 1:

Circuit performance with shifting the location of the optical board on the wafer (comparison result):

1. Continue with the file [[WDM_6_channel.icp]]. Go back to design mode and in [[temp_set_up.lsf]], update to -0.5 mm (-0.5e-3 m).
2. Run INTERCONNECT simulation and plot eye diagrams for the 6 channels and note the BER value in the Eye Diagram analyzer.
3. Go back to design mode and open and run the [[set_tunning_voltages.lsf]] script to set the best tuning voltage for the ring modulators and resonators at the current temperature.
4. Repeat step 2 and note the results.

The ring modulators and resonators in the circuit are designed with thermal tuning capabilities. The [[set_tuning_voltages.lsf]] script sets the tunning voltages of the rings based on their operating temperatures and with this thermal tuning, the rings performances are stable to temperature changes.

With the optical board placed on the origin of the wafer where the operating temperature is around 70 Celsius degrees. following are the eye diagrams and BERs for channel 1 without and with thermally tunning the ring models:

The ring modulator and resonator models show the tuning voltage and power of the rings. It takes about 0.022 W and 0.015 W to realign the ring modulator and resonator, respectively.

Updating the Model With Your Parameters

Instructions for updating the model based on your device parameters

Using new CMLs: The building blocks of the circuit comes from the Demo_CML which is based on the lumfoundry_template CML. User can replace the building blocks by models from other CMLs to generate the WDM circuit.

Customizing figure of merits: In this example we use BER and eye diagram of the channels as the figure of merit to decide the performance of the circuit. We noticed that with the thermal tuning of the ring modulators and resonators, we can tune the circuit to work relatively stable with temperature. In case of clean eyes with almost 0 BER, we can choose other figure of merits such as Error Vector Magnitude (EVM) as the criterion to determine the circuit performance.

Taking the Model Further

Information and tips for users that want to further customize the model

Full circuit optimization with multiple tools integration

In another example we have demoed the co-optimization of different Lumerical solvers with the optiSlang interoperability: Optimizing Traveling Wave MZM - optiSLang Interoperability . The workflow shown in this example can be adapted for an optiSlang-driven full circuit optimization, taking into account the thermal effect.

Use other test-bench circuits

This example uses a six-channel WDM transceiver as the performance test bench for temperature effect. But, it can be adapted for other circuits as well. You can create different test-bench simulation files that you can use depending on the results you want to extract.

Additional Resources

Additional documentation, examples and training material

See Also

• Wavelength division multiplexing
• Optimizing Traveling Wave MZM - optiSLang Interoperability

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