Lumerical supports numerous workflows with OptoCompiler for component level and circuit level design. You can import a layout and run component simulations in Lumerical, as well as run Lumerical INTERCONNECT as a simulation engine in OptoCompiler.
To facilitate custom component and circuit design, you can create custom INTERCONNECT CMLs such that they can be imported into the OptoCompiler schematic design environment.
For a custom INTERCONNECT CML to be usable in OptoCompiler, you must first install the CML in INTERCONNECT prior to simulation. Furthermore, certain views need to be created, and parameter mapping must be completed.
You can choose to manually create the views and map the parameters, or utilize the CML-Compiler-generated file “lib.defs”. The sections below detail both the automated and manual flows.
Automated Flow
This feature is available starting in 2026 R1.3.
In the CML Compiler GUI, you can select the Synopsys platform and generate the OptoCompiler library automatically by selecting the Symbol Generation option. The articles Editing Compact Model Library Properties and Library Master File provides instructions on how this through the GUI and the library master JSON file.
After building the CML, a “lib.defs” file is automatically generated as a part of the artifacts.
To use this CML, first install it in INTERCONNECT, and then, include the generated “lib.defs” file in OptoCompiler. See the article “Editing Library Definitions” within OptoCompiler help by searching “Library Definitions Editor” in the OptoCompiler in-product Help documentation for more information on how to include the “lib.defs” file.
Manual Flow
Prior to 2026 R1.3, the automatic generation of file “lib.defs” has not been enabled in CML Compiler. Follow the instructions below to set up the library manually.
Note: You still need to first install the CML in INTERCONNECT to use the generated models.
INTERCONNECT view
For the INTERCONNECT engine in OptoCompiler to create an optical netlist, you need an “INTERCONNECT” view for an element in OptoCompiler. This view can have the same geometric illustration to an existing “symbol” view for a component you wish to model.
As an example, the following shows an image with the 1x2 MMI used in the component design flow example.
Element parameter mapping
To associate the symbol with an INTERCONNECT model, you must also map the element parameters appropriately.
First, note down parameters for the INTERCONNECT element through the INTERCONNECT schematic environment, including the element name, port order, and parameters. You can enable the Port View tab using View->Windows->Port View from the top menu
After noting down the information above. Follow the instructions below to add INTERCONNECT parameters.
- Right-click the cell you wish to edit in the Library Manager tab, and press Edit Parameter Definitions, this opens a new Parameter Definition Editor tab.
- In the new Parameter Definition Editor tab, change the right-most dropdown from Effective to Base.
- Change to the Siminfo tab and add “INTERCONNECT” as a column.
After adding it as a column, follow the table below to enter information as needed. The table below contains parameters relevant for an INTERCONNECT model. You can add other parameters as necessary. Please refer to OptoCompiler documentation for further information.
| OptoCompiler parameter | Description |
| componentName | Specify the name of INTERCONNECT element as shown in INTERCONNECT Element Library. Most INTERCONNECT primitive element names include space character. Replace each space character using double underscore. For example: “CW Laser” should be “CW__Laser”. |
| instParameters | List all the parameters that INTERCONNECT model requires. |
| propMapping |
Provide the mapping between INTERCONNECT model parameters and OptoCompiler schematic parameters.
Note: This field is only required if parameter names between OptoCompiler and INTERCONNECT are different.
The format is as follows: nil <INTC parameter1> <OC parameter 1> <INTC parameter2> <OC parameter 2>… |
| termMapping |
Define the terminal name mapping.
Note: This field is only required if terminal names of the INTERCONNECT model are different from the OptoCompiler element. If they are the same, leave this field blank.
Use the following format: nil <OC terminal 1> <INTC terminal 1> <OC terminal 2> <INTC terminal 2>… |
| termOrder | Define the terminal order of the OptoCompiler schematic element. This must be the same as the INTERCONNECT terminal order. Otherwise, netlist connections will be out of order. |