The aim of this User Guide is to provide users with the basic information they need to get started on the KLayout & Lumerical layout-driven flows. For more background information on the KLayout & Lumerical design flows, please visit KLayout Interoperability Overview. This guide assumes that the user is familiar with circuit simulation using INTERCONNECT.
Before You Start:
Install KLayout Interoperability
For instructions on setting up the KLayout-Lumerical interoperability, please visit the Installation Instruction page.
Lumerical Installation Path Setup
Lumerical installation path is the user’s local path where Lumerical is installed. Setting up this path will ensure a stable integration between KLayout and Lumerical. It is recommended that users set up the Lumerical installation path upon the first time using the KLayout – Lumerical integration.
To specify the Lumerical installation path in KLayout, please follow the steps below:
- Open KLayout and find the Ansys Lumerical menu above the toolbox.
- Click on Ansys Lumerical > Environment Setup > Setup Lumerical Installation Path.
- Select the Lumerical version folder where INTERCONNECT is installed and click Select Folder.
This path will be saved permanently. To update the Lumerical installation path, please repeat the above steps.
Project Directory Setup
The project directory is the path to store layout files and temporary netlist files. Using the project directory would help users to track their simulation project.
To set up the project directory, please follow the steps below:
- Open KLayout and find Ansys Lumerical menu above the toolbox.
- Click on Ansys Lumerical > Environment Setup > Setup Project Directory.
- Select the desired folder and click Select Folder to confirm.
The directory path will be saved. To update the project directory path, please repeat the above steps.
Circuit Design in KLayout:
Create Optical Ports for Layout
Optical ports are required to create a netlist for a circuit. The ports are used to connect the desired ports of a circuit to sources and analyzers to simulate the behavior and performance of the circuit. Optical ports must be defined in KLayout by placing a text starting with ‘INTC_IO_’ on the components which are intended to work as optical IOs.
There are two ways of adding an optical port for a circuit in KLayout.
To use automated optical ports generation, please follow the steps below:
- Place the cursor on the desired pin of the component and record the coordinate reading on the bottom corner in KLayout window. Note: All ports must be placed on the pins. Otherwise, users will get a faulty netlist. (A pin is a box or circle shape on the ‘PinRec’ or 'FbrTgt' layer. All the components in the supported PDKs should have at least one pin.). In the image below, the coordinates read -618 and 152.
- Click Ansys Lumerical > Circuits Simulation > Add Optical Ports (Text Labels).
- Input the integer x and y coordinates, separated with a comma ‘,’. Then click OK.
- Input the port name (starting with ‘INTC_IO_’) in the new window then click OK.
- The optical port will be added at the desired location.
To manually add an optical port, please follow the following steps:
- Select layer Text in the Layers tab in the KLayout window.
- Then click the Text symbol in the KLayout Toolbox
- Edit the property Text in the Editor Options tab by inputting the port name starting with INTC_IO_
- Move the cursor to the desired pin and left click to instantiate the port. Note: All ports must be placed on the pins. Otherwise, users will get a faulty netlist. (A pin is a shape on ‘PinRec’ or 'FbrTgt' layer. All the components in the supported PDKs should have at least one pin.)
Export Circuits to INTERCONNECT
A netlist (.spi) file describes what circuit components are used in a circuit, what parameter values are used for those components, and how they are connected. A netlist file is required to translate the circuit layout in KLayout based on the PDK components to the INTERCONNECT circuit based on CML components.
Export "Top Cell" Circuit to INTERCONNECT
To simulate a circuit from KLayout, netlist of the circuit needs to be imported to INTERCONNECT. Circuits can be imported to INTERCONNECT automatically using the KLayout – INTERCONNECT integration. Before importing a circuit from KLayout to INTERCONNECT, please make sure:
- CMLs for the used KLayout PDK are properly installed in INTERCONNECT. For more information, please visit the Install Compact Model Library page.
- Optical ports are placed at the correct locations starting with ‘INTC_IO_’
To import the netlist from KLayout to INTERCONNECT, please follow the steps below:
- In Cell tab of KLayout, right click the circuit name and click on Show As New Top.
- Navigate to Ansys Lumerical in the menu tab and click Circuits Simulation > Export circuit to INTERCONNECT.
- In the prompt window, leave the two optional inputs as they are and click OK. These two inputs are optional for incremental design.
- In the prompt window, leave the two inputs as default and click OK
- Wait for a new INTERCONNECT session to be open, then view the circuit in INTERCONNECT
The ‘Test File’ and ‘Compound Element Name’ are optional for increment design. For more details, please refer to the Increment Design section below.
Export Multiple Circuits to INTERCONNECT
Multiple circuits can be selected in KLayout and imported to INTERCONNECT for simulation (shown below).
To import multiple circuits to INTERCONNECT, please follow the steps below:
- First, each circuit in the layout in KLayout needs to be formed into a cell.
- Selected all instances of one circuit in KLayout.
- In the KLayout menus, click Edit > Selection > Make Cell.
- Input a unique cell name for the selected circuit in the prompt window.
- Repeat above steps for other circuits
- Go to top cell view to view all circuits by right clicking the top cell > Show As New Top
- Hold the Shift key on keyboard and click the circuits one by one to select the circuits.
- Click on Ansys Lumerical > Circuits Simulation > Export circuits to INTERCONNECT
Export Netlist File
A netlist of a circuit in KLayout can also be extracted and saved to a user specified path for review. To do this, please follow the steps below:
- Place optical IOs on the desired components (see section Create optical ports for layout for more details).
- Navigate to Ansys Lumerical in the menu tab and click Circuits Simulation > Export Netlist.
- Type the file name and select a directory to save the netlist.
The netlist file is a .spi file which can be opened and viewed using Notepad by right click the netlist file > Open with > Notepad.
Create INTERCONNECT Testbench
Once the netlist has been imported, a test bench is built around the imported circuit (subcircuit) compound element to run a simulation. The test bench typically involves optical and electrical elements from INTERCONNECT’s Element Library including:
Here is an example of a test bench used to measure the gain spectra of a 4-channel WDM filter.
User can build a test bench either manually or automatically using scripts. Both the project file (.icp) or script file (.lsf) can be saved to reuse the test bench.
To create a test bench manually, please follow the steps below:
- In KLayout, import the circuit to INTERCONNECT using the method described in section Export circuit to INTERCONNECT above.
- In the new session of INTERCONNECT, set up the test bench by adding element from Element Library and making connections between added elements and your circuit.
- Save the project file (.icp) to reuse the test bench in incremental design (see section Incremental Design below).
To use a script file to set up a test bench, simply open the script file in Script File Editor and click run after importing netlist to INTERCONNECT.
To learn more about setting up a test bench with scripts, please refer to the SCRIPTING100.
Users can also build and save test benches using commands. Some useful commands are:
Note: as the subcircuit contains compact model library components, the compact model library must be installed before the test bench file can be successfully loaded.
Workflow for Incremental Design
The workflow of incremental design is shown below. In incremental design, users can update the sub-circuit in INTERCONNECT based on the simulation results, without rebuilding the testbench each time when importing the circuit from KLayout. The test bench files containing information about the circuit elements and connections can be saved and reused.
To perform incremental design and reuse the testbench file, please follow the steps below:
- In KLayout, draw circuit layout and place optical IOs on the desired components (see section Create optical ports for layout for more details).
- Navigate to Ansys Lumerical in the menu tab and click Circuits Simulation > Export circuit to INTERCONNECT.
- In the prompt window, load the pre-defined test bench file (.icp or .lsf)
- If the test bench file is an .icp project file, input the name of the circuit to be updated.
- If the test bench file is an .lsf script file, leave the Compound Element Name as "Default".
- Click OK to import the circuit and test bench into a new INTERCONNECT session
Note: The user will get an error if the Compound Element Name in the KLayout prompt window does not match the name of the circuit in the .icp project file.
Component Design Flow
Export Components to Lumerical Multiphysics Simulators
To generate the 3D geometry of your component from KLayout, the integration technology needs to use a process file be imported to the Lumerical Multiphysics simulators.
To export the component design from KLayout to Lumerical, please follow the steps below:
- Navigate to Ansys Lumerical in the menu tab and click Component Simulation > Export component
- In the prompt window, use the drop-down menu to select which simulator you wish to use.
- Use the “Load” button to select the process file.
- Use the drop-down menu to select which component to simulate. (Note that you can reduce the number of options in this list by selecting only the cell you wish to simulate before opening this menu. Please see “Selecting components for export” section below.)
- Click “OK” and wait for your simulation session to launch. You will then see the generated geometry in the simulator.
Selecting components for export
When you use the “Export components” button in the Ansys Lumerical menu tab, a list of all the cells and subcells will be generated from all levels below the Top Cell view. While users do have the option to export the whole circuit geometry to the Lumerical Multiphysics simulators, this is not recommended, as it will take extra time to generate the geometry for the entire circuit. Instead, it is recommended to only export the component that is to be simulated. You may find the component in the cell list from the top cell in the “Export components” window. Alternatively, before opening the export window, select only the component you wish to simulate. Now when you open the window, only that component will show up in the list.