KLayout interoperability is a layout driven simulation flow initiated by Professor Lukas Chrostowski from the University of British Columbia under the SiEPIC project. This interoperability includes several packages:
- SiEPIC-Tools: a package for integrated photonics layout, design, and verification.
- Ansys Lumerical: a dependent-package of SiEPIC-Tools. It allows users to directly export circuit layouts to INTERCONNECT for simulations.
Layout-driven circuit design flow
The diagram below shows the steps taken in INTERCONNECT as part of the KLayout & Lumerical layout driven flow.
- Circuit and system designers use KLayout to create their circuit layouts.
- Circuit netlists that describe the circuit components and connections can be generated in KLayout and imported to INTERCONNECT. A circuit will be generated based on the compact model library components with appropriate connections in a new INTERCONNECT session.
- Users can then create test benches, including sources and analyzers to simulate the behavior and performance of the circuit.
- Incremental design flow is supported where users can update the circuit design in KLayout, redo steps 2 and 3 with reusing the test benches that they have already defined.
Find installation instructions, licensing requirements and user guides in the following links of this page.