KLayout interoperability is a layout driven simulation flow initiated by Professor Lukas Chrostowski from the University of British Columbia under the SiEPIC project. This interoperability includes several packages:
- SiEPIC-Tools: a package for integrated photonics layout, design, and verification.
- Ansys Lumerical: a dependent-package of SiEPIC-Tools. It allows users to directly export component layouts to Lumerical Multiphysics Simulators, as well as circuit layouts to INTERCONNECT for circuit simulations.
Layout-driven circuit design flow
The diagram below shows the steps taken in INTERCONNECT as part of the KLayout & Lumerical layout driven circuit design flow.
- Circuit and system designers use KLayout to create their circuit layouts.
- Circuit netlists that describe the circuit components and connections can be generated in KLayout and imported to INTERCONNECT. A circuit will be generated based on the compact model library components with appropriate connections in a new INTERCONNECT session.
- Users can then create test benches, including sources and analyzers to simulate the behavior and performance of the circuit.
- Incremental design flow is supported where users can update the circuit design in KLayout, redo steps 2 and 3 with reusing the test benches that they have already defined.
Layout-driven component design flow
The list below describes the steps taken in KLayout and Lumerical Multiphysics Simulators as part of the KLayout & Lumerical layout-driven component design flow.
- Component designers use KLayout to create their component layouts.
- Components generated in KLayout can be imported to Lumerical’s Multiphysics Simulators using a process file with layer stack information. The 3D geometry of the component will automatically be generated in the simulators.
- Users can then configure their simulation region and ports, and run simulations to analyze the behavior of the component.
Find installation instructions, licensing requirements and user guides in the following links of this page.