This page demonstrates the electro-optical co-simulation workflow using Spectre-INTERCONNECT on the EPDA environment. For license and tools requirement and environment setup, please refer to the Tools & license requirement and Install EPDA environment to a new working directory pages.
Following are the detailed steps to setup and run Spectre-INTERCONNECT interop.
Add/Create Design Libraries
Please refer to the EPDA Optical Network Analysis (ONA) workflow for the first two steps on adding and creating design libraries. Sections:
- Add Design Libraries
- Create a Design Library
In this example, we are going to create a design library named "CoSim_example".
Create Schematic Design
With the first two steps finished, the "CoSim_example" library should be created. To create a circuit schematic design, click on the "CoSim_example" library and create a new cell named "testBench" with "schematic" type:
Click on "OK" and the Schematic Editor will be brought up. In the Schematic Editor, create an amplitude modulator (AM) circuit by going to:
Create -> Instance
and adding the "Optical_Amplitude_Modulator" cell from the "INTERCONNECTLib" library. The properties of the amplitude modulator can be left as default:
Then use the same method and add the "CWLaser", "PIN_Photodetector" components to the schematic editor and place them as shown below:
When adding the "PIN_Photodetector", set its noises (thermal and shot noises) to "false":
For the electrical driving signal, add "vsource" and "gnd" instances from the "analogLib" library, and set the "vsource" to be PRBS source type with 0.1 ns (100 ps) bit period:
Also add "res" and "gnd" instances to the output of the photodetector. The models can be laid out as shown below:
Then connect the models by using:
Create -> Wire (narrow)
The final schematic should look like below:
Check and save the schematic. Then, close the schematic editor.
Setup Netlist Config
After schematic design in the previous step, now we can set netlist partition rules.
Create the HED config view through "Library Manager" by:
File -> New -> Cell View
Set the View type to "config":
Click on "OK" and the "New Configuration" window will pop up. In the "New Configuration" window, click on the "Use Template" button and choose the "spectre" template from the drop down list, and click "OK".
In the Hierarchy Editor, navigate to "Top Cell" setup and set "Library", "Cell", and "View" options to be "CoSim_example", "testBench", and "schematic", respectively, which applies the netlist partition configuration on the circuit schematic design. Click on the “Recompute the hierarchy” button to update the setup.
The "Global Bindings" setup configures hierarchy expansion rules for circuit netlist. For more information, please refer to Cadence "Hierarchy Editor User Guide" or "Cell Bindings for netlist partition" in Appendix. In this example, add "INTERCONNECT" to the end of "View list" and set "Stop List" to "spectre".
Note that users do not need to create a HED config for optical netlist. Optical netlister automatically reuse the "View List" of config, in order to keep a consistent hierarchy expansion for both electrical netlist and optical netlist. The "Stop List" of optical netlist expansion is specified in the "Co-simulation Setup", which will be introduced in section Co-simulation setup.
HED config determines connecting nodes between electrical domain and optical domain. Electro-optical co-simulation is performed by exchanging data between electrical simulator (i.e. spectre/ams) and optical simulatior (i.e. INTERCONNECT) through these connecting nodes. For more information, please refer to Appendix: Co-simulation data communication.
Setup ADE maestro
Click on the "ADE Explorer" button in the "Hierarchy Editor" window and select "Create New View" in the pop-up "Launch ADE Explorer" window to bring up the "Create New ADE Explorer View" window.
Click on "OK" and the "ADE Explorer Editing" window will pop up.
Set Simulator
In "ADE Explorer Editing" window, set the simulator to "spectre" by going to:
Setup -> Simulator
Open Design in Tab
Right click on the "CoSim_example_testBench_1" entry and select "Open Design in Tab".
Set Analyses
Then go back to "maestro" tab and set the analyses by going to:
Analyses -> Choose
Set the analysis type to "tran" and set the simulation "Stop Time" to 3.2 ns. Check the "Enable" box.
Simulation outputs
Add a result to the maestro window by going to:
Outputs -> Add -> Signal
and set its name to "output". Double click on the "Details" entry to bring up the schematic design again, then select the "output" port of the PIN_Photodetector as the output.
Save the configured ADE Explorer window. The configured ADE explorer window is shown below:
Co-simulation setup
To setup the co-simulation properties for INTERCONNECT, users can go to
Setup -> INTERCONNECT -> Co-simulation Setup
A “INTERCONNECT Co-simulation setup” window will pop up. The details of the co-simulation settings are explained in Appendix: Co-simulation settings. For this example, the co-simulation setup is as shown below:
Setup Design Kits (optional)
User can also load the Compact Model Libraries (CMLs) to INTERCONNECT from Virtuoso. To do this, in the ADE explorer window go to:
Setup -> INTERCONNECT -> Design Kit setup
Then the INTERCONNECT Design Kit Setup window will pop up. User can specify paths to CML folders.
Notes:
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Netlist and Run
In the ADE Explorer Editing window, create/update the netlists of the circuit by selecting:
Simulation -> Netlist -> Create
The figures in below show the generated electrical and optical netlists, respectively.
Once the netlist can be generated successfully, perform co-simulation by:
Simulation -> Run
ADE will call out INTERCONNECT engine to perform optical simulation in backstage. User should see a pop-up log window indicating the status of the simulation and the time step information will be shown and updated in the “spectre.out” window, as shown in the figure in below.
View Results
Once co-simulation is completed, user can view the result by using virtuoso Result Browsers in:
Tools -> Results Browser
A visualizer similar to the figure in below will be shown. In the file navigator on the left, go into the result by clicking on the file-tree:
CoSim_example_testBench_1/psf -> tran -> net6
Select and plot the "net6" result under the "Signals" tab. Result will show on the result window on the right-hand side:
Appendix
Cell Bindings for netlist partition
"View List" is a list of views, specified in order of preference, for cells. For each cell, the first view in the list that is found is used. In other words, "View List" defines the hierarchy expansion rules for the electrical elements and optical elements.
The "Stop List" is the list of views to determine when the hierarchy expansion will stop and when a cell should be considered a leaf node in the hierarchy.
Co-simulation data communication
Electro-optical co-simulation is accomplished by allowing INTERCONNECT and Spectre to simulate their own, domain-specific representations, and communicate (bi-directionally, i.e., push and pull) simulation data between all the specific connecting nodes by using the Direct Programing Interface (DPI) and the Application Programming Interface (API). All the electrical pins of electro-optical (EO) components (i.e., having both electrical and optical ports) at the base level are automatically identified as connecting nodes between electrical and optical domains. This is automatically performed by our EPDA built-in algorithm based on HED config, which traverses down all the schematic hierarchies, stops at each EO component symbol at the base level, and generates data push/pull commands for its electrical ports depending on the port direction (“push” command is generated for “input” port, which push data from Spectre to INTERCONNECT; “pull” command is generated for “output” port, which pull data from INTERCONNECT to Spectre; Both “push” and “pull” commands are generated for “inputOutput” port).
Data communication automatically takes place behind the scene of co-simulation. User does not need to perform any setting.
Note that triggering co-simulation requires at least one "push" command in data communication. In other words, the co-simulation circuit design must have at least one electrical input or inputOutput port for its EO components.
Co-simulation settings for INTERCONNECT
An “INTERCONNECT Co-simulation setup” window contains the following settings:
- The "INTERCONNECT primitive view name(s)" will be auto-filled as "INTERCONNECT", which specifies "Stop List" for the optical netlist (In other applications, user can update this field based on the INTERCONNECT primitive view name(s) of PDKs components).
- The INTERCONNECT transient time window is automatically synchronized with the “Stop time” of Spectre “tran” analysis. Users need to set “Time Step” for INTERCONNECT, either through “user-defined” or “Use Spectre min step”.
- Clicking on the “Refresh” button will update the “Number of Samples” according to "Stop time" and "Time Step" settings.
- Make sure the “Enable Co-simulation?” box is checked before clicking “OK” to finish.
- Users can also check “Hide INTERCONNECT UI?” and “Hide INTERCONNECT splash window?” to hide the INTERCONNECT graphical user interface (UI) and splash window, respectively.
- User can select “delay insertion” option for INTERCONNECT Root Element, through the “delay insertion” setting in this Co-simulation setup window. For more information on the "delay insertion" settings, please refer to the Root Element page.
- “CML internal electrical equivalent” sets the “internal electrical equivalent” setting of INTERCONNECT Root Element. For more information on the "internal electrical equivalent" setting, please refer to the Root Element page. For an electro-optical (EO) element, if its electrical equivalent circuit is defined in Virtuoso, the internal electrical low pass filter (LPF) of its INTERCONNECT CML model should be turned off to not double count the electrical RC bandwidth. In this case the "CML internal electrical equivalent" needs to set to "false". However, if the electrical equivalent circuit is not defined in Virtuoso, the "CML internal electrical equivalent" can be set to "true" to capture the RC bandwidth for the EO element by enabling the internal electrical LPF of its INTERCONNECT CML models. Note that this is a global setting that applies to all the EO elements in the circuit.
Co-simulation sampling rates
Spectre can perform transient simulation in either adaptive sampling rate (by default) or a fixed sampling rate. INTERCONNECT perform transient simulation only in a fixed sampling rate. Co-simulation data communication automatically takes place at every Spectre's transient time step. In most cases, Spectre and INTERCONNECT can have different sampling rates for performing co-simulation. User can also synchronize Spectre and INTERCONNECT sample rates by forcing the Spectre "maxstep" and "minstep" equal to the INTERCONNECT "Time Step", as shown in below.
Probe optical signal
Users can probe the optical pins in the schematic and added them to the Outputs for visualization, or add monitors to the pins to automatically probe the signal.
Option 1: Probe optical pins from the schematic design
Outputs can be selected from the schematic design by double clicking on the “Details” entry and choosing the corresponding optical pins from the schematic.
For example, in the ADE Explorer Editing window, click on the “Add Outputs” button to add a new output entry and set the “Type” to be “signal”. Then double click on the “Details” entry to bring up the “Select from schematic” button.
Then in the schematic, click on the optical pin to add to the output.
Also note that optical data for selected pins can ONLY be visualized through Virtuoso Results Browser in:
Tools -> Results Browser
Option 2: Add optical monitors to probe signal
This feature is available in Lumerical 2022R2.2 and later. To use this feature, a user should open schematic design in the ADE Explorer by right clicking on the ADE testbench name and select Open Design in Tab.
Next, in the opened schematic right click on an optical port, select Set-up Optical Monitors and Monitor INTERCONNECT optical signal option. This would automatically add signal monitors to the ADE Output Panel to store the signal’s raw data, as well as set up expressions for extracting its optical power, phase, or gain. Then run the simulation and the results will be automatically plotted once the simulation completes.
Notes:
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Setup Electro-Optical Design Hierarchy
From release 2020 R2, electro-optical co-simulation start to support default single HED configuration for netlist generation. The single HED configuration is enabled by default under the "CIW > INTERCONNECT Interop > Electro-Optical Design Hierarchy" setup, as shown in below.
If users want to supply two HED configs for co-simulation (one for Spectre netlister and one for INTERCONNECRT netlister), they can disable the option in this setup and correspondingly supply an INTERCONNECT HED config to the "INTERCONNECT Co-simulation setup". In this case, the two HED configs must provide consistent connecting nodes between electrical and optical domains so that co-simulation data communication can be performed automatically.