Virtuoso interoperability - Optical network analysis (ONA)

This page will demonstrate photonics frequency domain simulation with Optical Network Analysis (ONA) on the EPDA design environment. For the environment setup and license and tools requirement, please see the Tools & license requirement and Install EPDA environment to a new working directory pages.

Following are the detailed steps to setup and run an EPDA frequency domain (ONA) simulation.

Add Design Libraries

Launch Virtuoso from your EPDA working directory. Open Library Manager by:

CIW -> Tools -> Library Manager

INTERCONNECTLib library

"INTERCONNECTLib" contains many primitive elements, and each element symbol is mapped to a corresponding INTERCONNECT primitive model through Virtuoso CDF setup. This library has been automatically added to Virtuoso Library Manager if EPDA environment has been properly installed. 

Load basic and opticalLib libraries

basic and opticalLib are two Virtuoso build-in libraries, and they must be loaded to enable optical schematic design. Add these two libraries to the Library tab by going to:

Edit -> Library Path

and navigating to the library directory. The prompt message in the pop-up Library Path Editor shows the steps for adding libraries. The basic and opticalLib libraries can be found in:

<virtuoso installation directory>/tools.lnx86/dfII/etc/cdslib/basic
<virtuoso installed directory>/tools.lnx86/dfII/etc/cdslib/opticalLib

Once the libraries are successfully installed, they will be shown in the Libraries tab and can be used in Virtuoso to create schematic designs.

Create a Design Library

In the Library tab, create a new design library for the ONA simulation by going to:

File -> New -> Library

and the New Library tab will open in the working directory. Key in the Library name "ONA_OTRAN_example" and click on the "OK" button to create the new library.

Create Schematic Design

Create a Compound

In the Library tab, click on the new library "ONA_OTRAN_example" and create a schematic cell view for the testbench by going to:

File -> New -> Cell View

Key in the Cell name "cascaded_ring" and select "Type" to be "schematic":

Click on "OK" and the Schematic Editor will be brought up. In the Schematic Editor create a cascaded single bus ring circuit by going to:

Create -> Instance

then find the "Single_Bus_Ring_Resonator" Cell from the "INTERCONNECTLib" library and set its properties as shown in the screenshot below:

"Hide" the window and add this instance to the Schematic Editor. Note with difference length and indices of the ring waveguide, the ring will have different resonance wavelegnth. Use the same method to add another instance of the "Single_Bus_Ring_Resonator" to the schematic, and with a different length of the ring this time:

When doing schematic design, user can create hierarchical structures like compounds. Before creating the compound, we need to define the pins that connect the inner components of the compound to the outside level schematic. To create pins, go to:

Create -> Pin

and create two optical pins according to the setting shown in below screenshot:

Layout the instances and pins as shown below:

and make connections between them by:

Create -> Wire (narrow)

Click on the ports to make the connections:

With the above internal circuit inside the compound defined, to create a symbol for compound, go to

Create -> Cellview -> From Cellview

to bring up the “CellView From Cellview” window, name the Cell as "cascaded_ring" and click on the “OK” button. 

In the pop-up "Symbol Generation Options" window, place the two pins "opt_in" and "opt_out" on the left and right, respectively.

Click on "OK" and a "Symbol Editor" window will be brought up. View and close off the symbol and schematic editors with save. The cell "cascaded_ring" will appear in the Cell tab.

Create Testbench Schematic

To create the schematic for the testbench, go back to the "ONA_OTRAN_example" library and create a new cell view named "testBench" with "schematic" type: 

In the Schematic Editor, instantiate the "cascaded_ring" element from the "ONA_OTRAN_example" library by "Add Instance":

After the fully creation of the schematic, users can do

Check -> Hierarchy

to check the hierarchy of the schematic and make corrections if needed. Then users can click on the save button to save the schematic.

Setup Netlist Config

After create the schematic, we can create a config view under the same testbench cell to configure circuit netlist. Set the Cell View type to "config":

Click on "OK" and the "New Configuration" window will pop up. Set the "View" to "schematic" to point the configuration to the testbench schematic. The "Global Bindings" setup configures hierarchy expansion rules for writing circuit netlist. For more information, please refer to Cadence "Hierarchy Editor User Guide". In this example, set "View List" to "schematic INTERCONNECT" and "Stop List" to "INTERCONNECT" as shown below:

Click on "OK" and save the "Hierarchy Editor".

Setup ADE

Click on the "ADE Explorer" button in the "Hierarchy Editor" window and select "Create New View" in the pop-up "Launch ADE Explorer" window to bring up the "Create New ADE Explorer View" window.

Click on "OK" and the "ADE Explorer Editing" window will pop up. 

Set Simulator

In "ADE Explorer Editing" window, double click on the "Simulator" entry and select "INTERCONNECT to be the simulator".

Open Design in Tab

Right click on the "ONA_OTRAN_example_testBench_1" entry and select "Open Design in Tab". 

Set Analyses and ONA Input

Then go back to "maestro" tab. Double click on the "Analyses" entry and config the analysis as shown below:

This Analysis form allows user to specify many ONA analysis properties and Root Element properties, e.g., frequency range and number of points. For more information, please refer to the ONA element page and Root Element page for the details of the ONA properties.

To set the "Input" for the ONA analysis, user can click on the "Select Input" button and select the "opt_in" port in the schematic design, or key in the input port name manually. Please note that the "Select Input" button can only be used if user has done "Open Design in Tab".

Set ONA outputs

Add a result to the maestro window by going to:

Outputs -> Add -> Signal

and set its name to "transmission". Double click on the "Details" entry to bring up the schematic design again, then select the "opt_out" port in the schematic as the output.

Save the configured ADE Explorer window. The configured ADE explorer window is shown below:

Setup DesignKit

User can also load the Compact Model Libraries (CMLs) to INTERCONNECT within Virtuoso. To do this, in the ADE explorer window go to:

Setup -> Design Kits

Then the INTERCONNECT Design Kit setup window will pop up and user can browse to the corresponding CML folders to add them to INTERCONNECT.

Netlist and Run

In the ADE Explorer Editing window, update INTERCONNECT netlist of the circuit by selecting:

Simulation -> Netlist -> Create

The figure in below shows the generated INTERCONNECT netlist.

Once the netlist can be generated successfully, perform ONA simulation by:

Simulation -> Run

ADE will call out INTERCONNECT engine to perform optical simulation in backstage. User should see a pop-up log window indicating the status of the simulation. Once the simulation is completed, “Simulation completed successfully” will be shown in the log window, as shown in the figure in below. 

View results

Once ONA simulation is completed, user can view the result by using virtuoso Result Browsers in:

Tools -> Results Browser

A visualizer similar to the figure in below will be shown. In the file navigator on the left, go into the result by clicking on the file-tree:

ona-ona -> I0 -> opt_out

Then select and plot the "mode 1" result in the "Signals" tab; then result will show on the  result window ont he right hand side: