This section discusses the simulation configuration for Sample Mode and Block Mode.
Sample Mode Simulation
Configuring a simulation to run using Sample Mode is equivalent to configuring element sources, such as sequence and pulse generators to run using Sample Mode. INTERCONNECT global properties and expressions allow for simultaneously setting all the sources to run using Sample Mode:
- Using the Property View, select Root Element. This is where INTERCONNECT global properties can be set.
- In the Property Tree, select ‘Simulation/Signal Mode/output signal mode’
- Set ‘output signal mode’ to ‘sample’
By using expressions, the value of the global property ‘output signal mode’ is assigned to different elements in the circuit, this means changing its value affects the values of the circuit elements. For example, a CW Laser element also has the ‘output signal mode’ property, and its expression is defined as ‘%output signal mode%’ (% delimiters must be used when a property name contains white spaces).
When configuring Sample Mode, you can also select how the sample mode optical frequency band, or the simulation bandwidth, will be defined. The global property ‘sample mode frequency band’ can be set as ‘automatic’ or ‘single’.
If ‘single’ is selected, the user can then enter the ‘sample mode center frequency’ value and the simulation bandwidth is now defined by the property ‘sample rate’ and ‘sample mode center frequency’. This means that optical channels generated by multiple optical sources will be placed inside the optical signal bandwidth defined by these properties, if the current optical channels don’t fit into the selected optical signal bandwidth an error message is generated and the simulation cannot continue. In this case, the user will have to adjust the simulation sample rate and center frequency to accommodate the optical channels. The advantage of the ‘single’ frequency band is that the user can set and has control over the exact value of the simulation center frequency. The disadvantage is that the user must adjust its value and the sample rate to make sure all optical channels in the simulation fit into a single band.
You can also control how INTERCONNECT resolves deadlock conditions during the simulation. An element is deadlock when it does not run or calculate any samples during the simulation. Typically, an element needs samples in all its input ports to run, otherwise is deadlocked. The global property ‘deadlock resolution’ allows the simulator to ‘ignore’ or ‘prevent’ deadlocks. If ‘prevent’ is selected, the user can select if initial delays will be inserted on every element output port or only on bidirectional ports. By inserting initial delays into the element ports, elements will be able to run the simulation since they have data in all their input ports.
If ‘ignore’ is selected, the user will have to make sure all the elements will run by using only unidirectional elements or adding data delays where appropriate. In the circuit bellow, the CW_1 element will run and generate samples at ‘output’ port, the simulator will then transfer samples to WGD_1 ‘port 1’, but WGD_1 ‘port 2’ does not have any samples, so WGD_1 cannot run, and it is deadlocked. The same applies to the remaining elements of the circuit.
The second option is to set the global property ‘deadlock resolution’ to ‘prevent’, in this case INTERCONNECT will prevent the deadlock condition by automatically inserting data delays, and the resolution is transparent to the user. The user can also control if the initial delays should be inserted in every port by setting the ‘delay insertion’ property to ‘output ports’ or only insert delays in bidirectional ports by selecting ‘bidirectional ports’.
By setting property ‘deadlock resolution’ to ‘prevent’, bidirectional propagation is now initialized by inserting the initial samples at the element ports, so the user does not have to explicitly add Data Delays elements between bidirectional connections. This additional samples are additional delays between connections, and for optical circuits they are equivalent to additional group delays. For resonant structures, this additional group delay will affect a device free spectral range (FSR).
Optical waveguide elements such as the Straight Waveguide (Element Library\Waveguides\Straight Waveguide) are modeled as delay line, and they allow for compensating for the delays introduced by the simulator. Property ‘delay compensation’ removes these unwanted delays from the internal delay model.
Block Mode Simulation
Equivalent to Sample Mode, configuring a simulation to run using Block Mode is equivalent to configuring element sources, such as sequence and pulse generators to run using Block Mode. INTERCONNECT global properties and expressions allow for simultaneously setting all the sources to run using Block Mode:
- Using the Property View, select Root Element. This is where INTERCONNECT global properties can be set.
- In the Property Tree, select ‘Simulation/Signal Mode/output signal mode’
- Set ‘output signal mode’ to ‘block
When configuring Block Mode, you can also select how many blocks will be generated by each element source by setting the property ‘number of output signals’. It gives INTERCONNECT the capability to run multiple iterations using Block Mode, and to handle bidirectional optical systems that require multiple iterations.
In Block Mode, the simulation sample rate is defined globally, but elements can define their own local sample rate and the simulator will handle the resampling and merging of different optical signal channels automatically.