Mode overlap and expansion calculations with datasets: Script commands “overlap”, “expand” and “expand2”, available in Python API, and Lumerical script language (Ansys Lumerical FDTD and Ansys Lumerical MODE), now accept rectilinear datasets as arguments. Previously, these commands only accepted d-card or monitor names as input. Now users can provide any mode data, as long as it is evaluated in a rectilinear mesh and stored in a dataset.
Ansys Lumerical FDTD
Improved memory efficiency for FDTD GPU simulations (Express mode) with PML boundaries: GPU simulations with PML boundaries now use roughly half the memory for the same system.
Enhanced performance for FDTD GPU simulations (Express mode): Improvements in the dipole source and auto-shutoff monitoring can increase the solver rate by up to 10% for small systems.
Improved meshing efficiency for FDTD simulation of large metastructures: When using multi-threading, the meshing time for flat structures with large number of elements, such as metalenses/metastructures, has reduced by about 20%. In addition, the meshing time scales approximately on par with the number of threads, i.e. when the size of the problem (e.g., the number of meta-atoms) and the number of threads scale by the same factor, the mesh time remains approximately constant.
New features for FDTD GPU simulations (Express mode): FDTD GPU simulations can use Dipole Sources and its option to record local fields. Enabling this option allows to record the electromagnetic fields around the dipole, as well as the “dipolepower” and “purcell” results. These results are necessary for applications such as fluorescence enhancement.
Ansys Lumerical INTERCONNECT
Improved Ansys Lumerical INTERCONNECT scheduler for simulations with sample-to-block conversion: The “Sample-to-block converter” element can now properly handle situations when the number of samples reaching the element is less than anticipated, e.g. due to elements that reduce the number of samples (such as the “Optical Modulator Measured”). Previously, the simulation was stopped with an error message as there was no output from the Sample-to-block converter. The INTERCONNECT scheduler now forces a restart to flush the converter's buffer so that data is propagated to the next element and the simulation continues.
Ansys Lumerical CML Compiler
New Verilog-A photonic model: Ansys Lumerical CML Compiler has a new ‘veriloga_custom_element’ photonic model. As the name suggests, this model can be used by CML Compiler users to create a photonic Verilog-A model for any unique, active or passive, custom element that is currently not supported by CML Compiler. Users can write their own Verilog-A code to define the input-output relationship for the element and let CML Compiler handle the rest (e.g., port convention, multi-channel support, encryption, etc.).