Virtuoso Layout Suite users can route optical waveguide using a waveguide connector PCell. The connector PCell comes with a modeSpec table for computing layout-dependent waveguide optical properties (neff, ng, D, loss, etc.). CML Compiler provides a waveguide connector compact model, which can operate with the waveguide connector PCell for performing layout-aware circuit simulation.
The figure below illustrates the use of waveguide connector PCell for layout design and simulation. Designers can perform schematic-driven layout using the waveguide connector PCell. Once the waveguide layout is implemented, designers can back-annotate layout-dependent PCell parameter values to the circuit schematic. Next, using Virtuoso-INTERCONNECT EPDA workflow, the Virtuoso circuit schematic is transferred to Lumerical INTERCONNECT circuit solver, where the waveguide connector model is instantiated with the layout-dependent PCell parameters. When circuit simulation is initiated, the waveguide connector model would call Virtuoso connector PCell database, enquire about the optical waveguide properties for given layout-dependent PCell parameters at the simulation wavelength and temperature, and set the waveguide’s optical response accordingly.
Lumfoundry Templates: wg_connector
Quality Assurance Test: waveguide_connector QA
Statistical Modeling Support: No
Supported Parameters: Same as Virtuoso waveguide connector PCell.
Interoperability with Cadence Virtuoso:
- Circuit design flows using INTERCONNECT model: Yes.
- Circuit design flow using photonic Verilog-A model: No.
Support Matrix for Software:
Virtuoso Version | Lumerical Suite Version |
---|---|
IC23.10.020 ISR2 or later |
2023 (R2.3 or later) |